公开(公告)号：US08161338B2

公开(公告)日：2012-04-17

申请号：US11580650

申请日：2006-10-13

申请人： Janusz Rajski ,  Wojciech Rajski

发明人： Janusz Rajski ,  Wojciech Rajski

IPC分类号： G01R31/3177 ,  G01R31/40

CPC分类号： G01R31/318547

摘要： Exemplary embodiments of a compactor for compacting test responses are disclosed. In certain embodiments, the compactor comprises circular registers and has multiple inputs. The circular registers can have lengths that are relatively prime or prime. In certain implementations, the compactors are able to detect errors commonly observed from real defects, such as errors of small multiplicity and burst errors. Certain embodiments of the compactor operate according to modular arithmetic. Furthermore, because circular registers do not multiply errors or unknown states, embodiments of the disclosed compactors can tolerate one or more unknown states or at least exhibit a desirably high tolerance of such states.

摘要翻译： 公开了用于压实测试响应的压实机的示例性实施例。 在某些实施例中，压实机包括圆形寄存器并具有多个输入。 循环寄存器可以具有相对于素数或素数的长度。 在某些实施方案中，压实机能够检测通常从实际缺陷观察到的错误，例如小的多重性和突发错误的误差。 压实机的某些实施例根据模数运算进行操作。 此外，由于循环寄存器不会乘以错误或未知状态，所公开的压实机的实施例可以容忍一个或多个未知状态或者至少表现出对这种状态的期望的高容限。

公开(公告)号：US08046653B2

公开(公告)日：2011-10-25

申请号：US12854786

申请日：2010-08-11

申请人： Janusz Rajski ,  Grzegorz Mrugalski ,  Dariusz Czysz ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Grzegorz Mrugalski ,  Dariusz Czysz ,  Jerzy Tyszer

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/31921 ,  G01R31/318335

摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

摘要翻译： 以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。 所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。 其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

公开(公告)号：US08024387B2

公开(公告)日：2011-09-20

申请号：US11894393

申请日：2007-08-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F7/58

CPC分类号： G06F7/584 ,  G06F2207/583 ,  H03K3/84

摘要： Method and apparatus for synthesizing high-performance linear finite state machines (LFSMs) such as linear feedback shift registers (LFSRs) or cellular automata (CA). Given a characteristic polynomial for the circuit, the method obtains an original LFSM circuit such as a type I or type II LFSR. Feedback connections within the original circuit are then determined. Subsequently, a number of transformations that shift the feedback connections can be applied in such a way that properties of the original circuit are preserved in a modified LFSM circuit. In particular, if the original circuit is represented by a primitive characteristic polynomial, the method preserves the maximum-length property of the original circuit in the modified circuit and enables the modified circuit to produce the same m-sequence as the original circuit. Through the various transformations, a modified LFSM circuit can be created that provides higher performance through shorter feedback connection lines, fewer levels of logic, and lower internal fan-out.

摘要翻译： 用于合成诸如线性反馈移位寄存器（LFSR）或细胞自动机（CA）的高性能线性有限状态机（LFSM）的方法和装置。 给定电路的特征多项式，该方法获得原始的LFSM电路，如I型或II型LFSR。 然后确定原始电路内的反馈连接。 随后，可以以使原始电路的特性保留在修改的LFSM电路中的方式来应用移动反馈连接的多个变换。 特别地，如果原始电路由原始特征多项式表示，则该方法保留修改电路中原始电路的最大长度特性，并使修改电路能够产生与原始电路相同的m序列。 通过各种转换，可以创建一个修改后的LFSM电路，通过较短的反馈连接线路提供更高的性能，更低的逻辑电平和更低的内部扇出。

公开(公告)号：US20110214026A1

公开(公告)日：2011-09-01

申请号：US13013712

申请日：2011-01-25

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Mark Kassab ,  Nilanjan Mukherjee

IPC分类号： G06F11/25

CPC分类号： G01R31/318547

摘要： A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

摘要翻译： 在测试电路中将测试图案应用于扫描链的方法。 该方法包括提供比特的压缩测试模式; 将压缩的测试图案解压缩为被提供的压缩测试图案的解压缩测试图案; 以及将解压缩的测试图案应用于扫描电路被测电路。 取决于要生成解压缩位的方式，以相同或不同的时钟速率同步地执行提供压缩测试模式，解压缩压缩测试模式和应用解压缩模式的动作。 执行解压缩的电路包括解压缩器，例如适于接收压缩的位测试模式的线性有限状态机。 解压缩器将压缩的测试模式正在接收时，将测试模式解压缩为解压缩的位测试模式。

公开(公告)号：US07984354B2

公开(公告)日：2011-07-19

申请号：US12494121

申请日：2009-06-29

申请人： Dhiraj Goswami ,  Kun-Han Tsai ,  Mark Kassab ,  Janusz Rajski

发明人： Dhiraj Goswami ,  Kun-Han Tsai ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318547 ,  G01R31/318583

摘要： Improved responses can be generated to scan patterns (e.g., test patterns) for an electronic circuit designs having timing exception paths by more accurately determining the unknown values that propagate to observation points in the circuit, where the response is captured. For instance, the responses are determined more accurately by analyzing the effect of sensitizing a timing exception path during each time frame associated with a scan pattern. Path sensitization can be determined based on observing whether values injected at starting points of the timing exception paths due to signal transitions and glitches propagate to their end points. The response can be updated by masking the affected end points and propagating unknown values further in the circuit to determine whether they are captured at observation points of the circuit. For instance, the methods and systems described herein may result in reduced unknowns, improved test coverage and test compression.

摘要翻译： 可以通过更准确地确定传播到电路中观测点的未知值（其中捕获响应）的具有定时异常路径的电子电路设计来扫描模式（例如，测试模式）的改进的响应。 例如，通过分析在与扫描模式相关联的每个时间帧期间对定时异常路径敏感的影响，更准确地确定响应。 可以基于观察由于信号转换和毛刺传播到它们的端点而在定时异常路径的起始点处注入的值是否可以确定路径敏化。 可以通过在电路中屏蔽受影响的端点和进一步传播未知值来更新响应，以确定它们是否在电路的观测点被捕获。 例如，本文描述的方法和系统可以导致未知数减少，改进的测试覆盖和测试压缩。

公开(公告)号：US20110166818A1

公开(公告)日：2011-07-07

申请号：US13049844

申请日：2011-03-16

申请人： Xijiang Lin ,  Dariusz Czysz ,  Mark Kassab ,  Grzegorz Mrugalski ,  Janusz Rajski ,  Jerzy Tyszer

发明人： Xijiang Lin ,  Dariusz Czysz ,  Mark Kassab ,  Grzegorz Mrugalski ,  Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G06F19/00

CPC分类号： G01R31/318575

摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to reduce power consumption during integrated circuit testing. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) architecture). Among the disclosed embodiments are integrated circuits having programmable test stimuli selectors, programmable scan enable circuits, programmable clock enable circuits, programmable shift enable circuits, and/or programmable reset enable circuits. Exemplary test pattern generation methods that can be used to generate test patterns for use with any of the disclosed embodiments are also disclosed.

摘要翻译： 以下公开了用于在集成电路测试期间降低功耗的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）架构）集成。 在所公开的实施例中，具有可编程测试刺激选择器，可编程扫描使能电路，可编程时钟使能电路，可编程移位使能电路和/或可编程复位使能电路的集成电路。 还公开了可以用于产生用于与任何所公开的实施例一起使用的测试图案的示例性测试图形生成方法。

公开(公告)号：US20100083063A1

公开(公告)日：2010-04-01

申请号：US12633601

申请日：2009-12-08

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US07669101B2

公开(公告)日：2010-02-23

申请号：US12117701

申请日：2008-05-08

申请人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

发明人： Jon Udell ,  Chen Wang ,  Mark Kassab ,  Janusz Rajski

IPC分类号： G01R31/28

CPC分类号： G01R31/318314

摘要： Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e.g., parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

摘要翻译： 这里描述了用于分布式执行电路测试算法或其部分的方法和系统。 分布式处理可以加快处理速度。 彼此独立的算法或算法的部分可以以多个处理器的网络上的非连续方式（例如，并行）来执行。 该网络包括一个控制处理器，可以将任务分配给其他处理器，并自行执行某些任务。 依赖算法或其部分可以以顺序方式在控制处理器或受控处理器之一上执行。 对于本质上具有高度连续性的算法，可以修改算法的部分，以通过创建迭代的独立任务的滚动窗口来延迟对算法部分之间的依赖结果的需求。

公开(公告)号：US07647540B2

公开(公告)日：2010-01-12

申请号：US11880192

申请日：2007-07-19

申请人： Janusz Rajski ,  Grzegorz Mrugalski ,  Dariusz Czysz ,  Jerzy Tyszer

发明人： Janusz Rajski ,  Grzegorz Mrugalski ,  Dariusz Czysz ,  Jerzy Tyszer

IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F17/50 ,  G06G7/48

CPC分类号： G01R31/318547 ,  G01R31/318335

摘要： Disclosed below are representative embodiments of methods, apparatus, and systems used to generate test patterns for testing integrated circuits. Embodiments of the disclosed technology can be used to provide a low power test scheme and can be integrated with a variety of compression hardware architectures (e.g., an embedded deterministic test (“EDT”) environment). Certain embodiments of the disclosed technology can reduce the switching rates, and thus the power dissipation, in scan chains with no hardware modification. Other embodiments use specialized decompression hardware and compression techniques to achieve low power testing.

摘要翻译： 以下公开了用于产生用于测试集成电路的测试图案的方法，装置和系统的代表性实施例。 所公开的技术的实施例可以用于提供低功率测试方案，并且可以与各种压缩硬件架构（例如，嵌入式确定性测试（“EDT”）环境）集成。 所公开的技术的某些实施例可以在没有硬件修改的情况下降低扫描链中的开关速率，从而降低功耗。 其他实施例使用专门的减压硬件和压缩技术来实现低功率测试。

公开(公告)号：US20090187800A1

公开(公告)日：2009-07-23

申请号：US12412267

申请日：2009-03-26

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。