Motor Vehicle Brake System Having A Low Pressure Accumulator
    31.
    发明申请
    Motor Vehicle Brake System Having A Low Pressure Accumulator 有权
    具有低压蓄能器的汽车制动系统

    公开(公告)号:US20100045099A1

    公开(公告)日:2010-02-25

    申请号:US12307797

    申请日:2007-07-11

    CPC classification number: B60T8/4059

    Abstract: A motor vehicle brake system having a hydraulic cable, via which a wheel brake module can be pressurized by a brake medium using brake pressure from a brake cylinder and to which a low pressure accumulator is connected for temporarily receiving excess brake medium, wherein the low pressure accumulator is connected to the hydraulic cable via a backflow line and a return pump interposed in the return line in order to return temporarily stored brake medium, the return pump being cyclically actuated for adjusting the pump capacity such that an activation occurs within each braking cycle during a portion of pump cycles that corresponds to the pump capacity, is intended to provide particularly high operational safety while also providing a comfortable pedal sensation.

    Abstract translation: 一种具有液压电缆的机动车辆制动系统,通过该液压电缆可以利用来自制动缸的制动压力由制动介质对车轮制动模块进行加压,并且连接有低压蓄能器以临时容纳多余的制动介质,其中低压 蓄能器通过回流管路和回流泵连接到液压电缆,以便返回临时存储的制动介质,回流泵循环地致动以调节泵的容量,使得在每个制动循环期间发生激活 与泵容量相对应的泵循环的一部分旨在提供特别高的操作安全性,同时还提供舒适的踏板感觉。

    Data storage configuration having a display device
    32.
    发明授权
    Data storage configuration having a display device 有权
    具有显示装置的数据存储配置

    公开(公告)号:US07140547B2

    公开(公告)日:2006-11-28

    申请号:US10609884

    申请日:2003-06-30

    CPC classification number: G06K19/07703 G06K19/077

    Abstract: A portable data storage configuration has a card base and a display device, the display device being fixed to the card base. The display device is only partially connected to the card base by the fixed connection. This mounting technique results in that almost no lateral or shear forces act on the display device.

    Abstract translation: 便携式数据存储配置具有卡片基座和显示装置,显示装置固定在卡片基座上。 显示装置仅通过固定连接部分地连接到卡片基座。 这种安装技术导致几乎没有横向或剪切力作用在显示装置上。

    Test configuration for the functional testing of a semiconductor chip
    33.
    发明授权
    Test configuration for the functional testing of a semiconductor chip 失效
    用于半导体芯片的功能测试的测试配置

    公开(公告)号:US06825682B2

    公开(公告)日:2004-11-30

    申请号:US09826594

    申请日:2001-04-05

    Abstract: A test configuration for the functional testing of a semiconductor chip is described. The semiconductor chip, which can be subjected to a functional test for the purpose of checking the functionality of the semiconductor chip, is disposed on a support material. The semiconductor chip contains a self-test unit for generating test information and for carrying out the functional test. An energy source serves for providing an electrical energy supply from energy that is fed in contactlessly. The energy source is disposed on the support material and is connected to the semiconductor chip for the purpose of providing an energy supply on the semiconductor chip. The test configuration makes it possible to carry out a contactless functional test and to reduce the test costs by virtue of high parallelism during the functional test of a plurality of semiconductor chips.

    Abstract translation: 描述了用于半导体芯片的功能测试的测试配置。 可以进行用于检查半导体芯片的功能的功能测试的半导体芯片设置在支撑材料上。 半导体芯片包含用于产生测试信息和进行功能测试的自检单元。 能量源用于从能够无接触地馈送的能量提供电能。 能量源设置在支撑材料上并且连接到半导体芯片以便在半导体芯片上提供能量供应。 测试配置使得可以执行非接触式功能测试并且在多个半导体芯片的功能测试期间由于高并行性而降低测试成本。

    System for testing fast integrated digital circuits, in particular semiconductor memory modules
    34.
    发明授权
    System for testing fast integrated digital circuits, in particular semiconductor memory modules 失效
    用于测试快速集成数字电路的系统,特别是半导体存储器模块

    公开(公告)号:US06721904B2

    公开(公告)日:2004-04-13

    申请号:US09907693

    申请日:2001-07-18

    CPC classification number: G11C29/12015 G11C29/48 G11C29/56012

    Abstract: The invention relates to a system for testing fast integrated digital circuits, in particular semiconductor modules, such as for example SDRAMs. In order to achieve the necessary chronological precision in the testing even of DDR-SDRAMs, with at the same time the high degree of parallelism of the test system required for mass production, an additional semiconductor circuit module (BOST module) is inserted into the signal path between a standard testing device and the SDRAM to be tested. This additional module is set up so as to multiply the relatively slow clock frequency of the conventional testing device, and to determine the signal sequence for control signals, addresses, and data background with which the SDRAM module is tested, dependent on signals of the testing device and also on register contents, programmed before the test, in the BOST module.

    Abstract translation: 本发明涉及一种用于测试快速集成数字电路,特别是半导体模块(例如SDRAM)的系统。 为了在DDR-SDRAM的测试中实现必要的按时间顺序的精度,同时大规模生产所需的测试系统的高度并行性,将额外的半导体电路模块(BOST模块)插入到信号中 标准测试设备和要测试的SDRAM之间的路径。 该附加模块被设置为乘以常规测试设备的相对较慢的时钟频率,并且根据测试信号来确定用于测试SDRAM模块的控制信号,地址和数据背景的信号序列 设备以及在测试前编程的寄存器内容,在BOST模块中。

    Focusing hood for use on a digital camera
    35.
    发明授权
    Focusing hood for use on a digital camera 失效
    聚焦罩用于数码相机

    公开(公告)号:US06687460B2

    公开(公告)日:2004-02-03

    申请号:US09959325

    申请日:2001-12-04

    Applicant: Jochen Müller

    Inventor: Jochen Müller

    CPC classification number: G03B13/02 H04N5/2251

    Abstract: A telescopically extendible focusing hood which improves the viewing of the LCD screen of a digital camera in bright surrounding light. The focusing hood can be fixed to the rear wall of the camera, surrounding the LCD screen. The focusing hood preferably has an anti-reflection-coated enlarging lens or glass disk which covers the entire cross-section of the focusing hood in parallel to the fixing plane. In its extended state, the focusing hood can be used with a single lens in the manner of a 35 mm camera finder. When the enlarging lens is pushed in, the focusing hood can be used with two lenses for assessing the image.

    Abstract translation: 可伸缩聚焦罩,可在明亮的周围光线下改善数码相机液晶显示屏的观看。 聚焦罩可以固定在相机的后壁,围绕LCD屏幕。 聚焦罩优选具有平行于固定平面覆盖聚焦罩整个横截面的抗反射涂覆放大镜或玻璃盘。 在其延伸状态下,聚焦罩可以以35mm摄像机的方式与单个镜头一起使用。 当放大镜头被推入时,聚焦罩可以与两个透镜一起使用以评估图像。

    Integrated semiconductor memory device

    公开(公告)号:US06560149B2

    公开(公告)日:2003-05-06

    申请号:US10084134

    申请日:2002-02-27

    Applicant: Jochen Müller

    Inventor: Jochen Müller

    CPC classification number: G11C29/787

    Abstract: An integrated semiconductor memory device that can be subjected to a memory cell test in order to determine functional and defective memory cells includes addressable normal memory cells, a first redundancy unit having first addressable redundant memory cells and optically programmable switches for replacing an address of a defective normal memory cell by the address of a first redundant memory cell, and a second redundancy unit having second addressable redundant memory cells and electrically programmable switches for replacing an address of a defective normal memory cell by the address of a second redundant memory cell. The second redundancy unit can be connected by the activation of an irreversibly programmable switch, which enables a simplified functional test at the wafer level.

    Fusible link configuration in integrated circuits
    37.
    发明授权
    Fusible link configuration in integrated circuits 有权
    集成电路中的可熔链路配置

    公开(公告)号:US06407586B2

    公开(公告)日:2002-06-18

    申请号:US09781813

    申请日:2001-02-12

    CPC classification number: H01L23/5258 H01L2924/0002 H01L2924/00

    Abstract: The invention relates to a fusible link configuration in or on integrated circuits, in particular highly integrated memory chips, in which in each case one bank of fusible links (F1, F2, . . . ), together with an evaluation logic unit is configured beside and in association with a memory field segment. The evaluation logic unit is electrically connected to the fusible links (F1, F2, . . . ) and determines whether one or more of the fusible links (F1, F2, . . . ) is severed. One or more banks of the fusible links (F1, F2, . . . ) are divided up into smaller units while restricting the width(s) of the bank or banks. The units are grouped such that at least some of the fusible links (F1, F2, . . . ) are located beside one another transversely with respect to the width direction of the bank.

    Abstract translation: 本发明涉及集成电路中或其上的可熔链路配置,特别是高度集成的存储器芯片,其中在每种情况下,一组可熔链路(F1,F2,...)以及评估逻辑单元被配置在旁边 并且与存储器区段相关联。 评估逻辑单元电连接到可熔链路(F1,F2 ...),并确定是否断开了一个或多个可熔链路(F1,F2 ...)。 一个或多个可熔链节(F1,F2 ...)被划分成更小的单位,同时限制银行或银行的宽度。 这些单元被分组成使得至少一些可熔链节(F1,F2 ...)相对于堤的宽度方向横向彼此相邻。

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