公开(公告)号：US20190326257A1

公开(公告)日：2019-10-24

申请号：US15960937

申请日：2018-04-24

Applicant: Rahul Agarwal ,  Milind S. Bhagavat ,  Lei Fu

Inventor： Rahul Agarwal ,  Milind S. Bhagavat ,  Lei Fu

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498

Abstract: Various fan-out devices are disclosed. In one aspect, a semiconductor chip device is provided that includes a redistribution layer structure that has plural conductor structures and plural glass interlevel dielectric layers. A glass encapsulant layer is positioned on the redistribution layer structure. A first semiconductor chip and a second semiconductor chip are positioned in the glass encapsulant layer and electrically connected by at least some of the conductor structures. A cap layer is on the encapsulant layer.

公开(公告)号：US20190189590A1

公开(公告)日：2019-06-20

申请号：US15844575

申请日：2017-12-17

Applicant: Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

Inventor： Rahul Agarwal ,  Kaushik Mysore Srinivasa Setty ,  Milind S. Bhagavat ,  Brett P. Wilkerson

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L25/0657 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/10

Abstract: Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device includes a stack of plural semiconductor chips. Each two adjacent semiconductor chips of the plural semiconductor chips is electrically connected by plural interconnects and physically connected by a first insulating bonding layer. A first stack of dummy chips is positioned opposite a first side of the stack of semiconductor chips and separated from the plural semiconductor chips by a first gap. Each two adjacent of the first dummy chips are physically connected by a second insulating bonding layer. A second stack of dummy chips is positioned opposite a second side of the stack of semiconductor chips and separated from the plural semiconductor chips by a second gap. Each two adjacent of the second dummy chips are physically connected by a third insulating bonding layer. The first, second and third insulating bonding layers include a first insulating layer and a second insulating layer bonded to the first insulating layer. An insulating layer is in the first gap and another insulating layer is in the second gap.

公开(公告)号：US20100087123A1

公开(公告)日：2010-04-08

申请号：US12631929

申请日：2009-12-07

Applicant: Roland R. Vandamme ,  Milind S. Bhagavat

Inventor： Roland R. Vandamme ,  Milind S. Bhagavat

IPC: B24B49/04 ,  B24B7/17

CPC classification number: B24B37/28 ,  B24B7/228 ,  B24B49/02

Abstract: A method of processing a semiconductor wafer using a double side grinder of the type that holds the wafer in a plane with a pair of grinding wheels and a pair of hydrostatic pads. The method includes measuring a distance between the wafer and at least one sensor and determining wafer nanotopology using the measured distance. The determining includes using a processor to perform a finite element structural analysis of the wafer based on the measured distance.

Abstract translation: 使用将晶片保持在具有一对砂轮的平面中的类型的双面研磨机和一对静压垫来处理半导体晶片的方法。 该方法包括测量晶片与至少一个传感器之间的距离并使用所测量的距离来确定晶片纳米拓扑。 确定包括使用处理器基于测量的距离来执行晶片的有限元结构分析。

公开(公告)号：US06613591B1

公开(公告)日：2003-09-02

申请号：US10092479

申请日：2002-03-07

Applicant: Milind S. Bhagavat ,  Yun-Biao Xin ,  Gary L. Anderson ,  Brent F. Teasley

Inventor： Milind S. Bhagavat ,  Yun-Biao Xin ,  Gary L. Anderson ,  Brent F. Teasley

IPC: H01L2100

CPC classification number: B24B37/005 ,  B24B37/042 ,  B24B49/00

Abstract: A method for estimating the likely waviness of a wafer after polishing based upon an accurate measurement of the waviness of the wafer in an as-cut condition, before polishing. The method measures the thickness profile of an upper and lower wafer surface to construct a median profile of the wafer in the direction of wiresaw cutting. The median surface is then passed through an appropriate Gaussian filter, such that the warp of the resulting profile estimates whether the wafer will exhibit unacceptable waviness in a post-polished stage.

Abstract translation: 一种用于在抛光之前基于精确测量晶片在切割条件下的波纹度来估计抛光后晶片的可能波纹度的方法。 该方法测量上下晶片表面的厚度分布，以在切线方向上构建晶片的中间轮廓。 然后将中间表面通过适当的高斯滤波器，使得所得轮廓的翘曲估计晶片在后抛光阶段是否将呈现不可接受的波纹。