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公开(公告)号：US20150169479A1
公开(公告)日：2015-06-18
申请号：US14631748
申请日：2015-02-25
Applicant: Netronome Systems, Inc.
Inventor： Gavin J. Stark
CPC classification number: G06F13/287 , G06F7/10 , G06F9/34 , G06F9/467 , G06F12/00 , G06F13/00 , G06F13/4234 , G06F17/30 , Y02D10/14 , Y02D10/151
Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value is indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.
Abstract translation: 事务存储器（TM）从处理器接收总线上的查找命令。 该命令包括存储器地址，起始位位置和掩码大小。 响应该命令，TM拉动输入值（IV）。 存储器地址用于从存储器读取包含多个结果值（RV）和多个键值的单词。 每个键值表示由TM输出的单个RV。 TM内的选择电路使用起始位位置和掩码大小来选择IV的一部分。 IV的部分是关键选择器值。 基于键选择器值选择键值。 基于键值选择RV。 键值由键选择电路选择。 RV由结果值选择电路选择。
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公开(公告)号：US20150089242A1
公开(公告)日：2015-03-26
申请号：US14037319
申请日：2013-09-25
Applicant: Netronome Systems, Inc.
Inventor： Gavin J. Stark
IPC: H04L9/08
CPC classification number: G06F7/58
Abstract: An entropy storage ring includes an input node, a plurality of serial-connected stages, and an output node. Each stage includes an XOR (or XNOR) circuit, a delay element having an input coupled to the XOR output, and a combinatorial circuit having an output coupled to a second input of the XOR. The combinatorial circuit may be a NAND, NOR, AND or OR gate. A first input of the XOR is the data input of the stage. The output of the delay element is the data output of the stage. A first input of the combinatorial circuit is coupled to receive an enable bit from a configuration register. A second input of the combinatorial circuit is coupled to the ring output node. In operation, a bit stream is supplied onto the ring input node. Feedback of multiple stages are enabled so that the bit stream undergoes complex permutation as it circulates.
Abstract translation: 熵存储环包括输入节点，多个串联级和输出节点。 每个级包括XOR（或XNOR）电路，具有耦合到XOR输出的输入的延迟元件，以及具有耦合到XOR的第二输入的输出的组合电路。 组合电路可以是NAND，NOR，或或或门。 XOR的第一个输入是舞台的数据输入。 延迟元件的输出是级的数据输出。 组合电路的第一输入被耦合以从配置寄存器接收使能位。 组合电路的第二输入耦合到环形输出节点。 在操作中，位流被提供到环形输入节点上。 启用多级的反馈，使得位流在其循环时经历复杂的置换。
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公开(公告)号：US20150089095A1
公开(公告)日：2015-03-26
申请号：US14037214
申请日：2013-09-25
Applicant: Netronome Systems, Inc.
Inventor： Gavin J. Stark
CPC classification number: G06F12/063 , G06F3/061 , G06F3/0656 , G06F3/0683 , G06F9/3004 , G06F9/3836 , G06F9/467 , G06F2212/251 , H04L45/74
Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).
Abstract translation: 事务存储器（TM）包括控制电路管线和相关联的存储器单元。 存储单元存储多个环。 对于每个环，流水线保持头指针和尾指针。 管道的环操作阶段将维护指针，因为值被放置在环上并被取消。 如果环未满，则put命令会使TM将值放入环中。 如果环不为空，则get命令使TM取环， 如果环具有至少预定量的可用缓冲空间，则具有低优先级命令的put将导致TM将值放入环中。 从一组ring命令获取，使TM从最高优先级非空环（指定的一组环）获取一个值。
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公开(公告)号：US12223418B1
公开(公告)日：2025-02-11
申请号：US14841722
申请日：2015-09-01
Applicant: Netronome Systems, Inc.
Inventor： Nicolaas J. Viljoen
Abstract: A flow of packets is communicated through a data center. The data center includes multiple racks, where each rack includes multiple network devices. A group of packets of the flow is received onto a first network device. The first device includes a neural network. The first network device generates a neural network feature vector (NNFV) based on the received packets. The first network device then sends the NNFV to a second network device. The second device uses the NNFV to determine a set of weight values. The weight values are then sent back to the first network device. The first device loads the weight values into the neural network. The neural network, as configured by the weight values, then analyzes each of a plurality of flows received onto the first device to determine whether the flow likely has a particular characteristic.
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35.发明授权公开(公告)号：US10911038B1
公开(公告)日：2021-02-02
申请号：US16247566
申请日：2019-01-15
Applicant: Netronome Systems, Inc.
Inventor： Gavin J. Stark , Steven W. Zagorianakos , Ronald N. Fortino
Abstract: A network flow processor integrated circuit includes a plurality of processors, a plurality of multi-threaded transactional memories (MTMs), and a configurable mesh posted transaction data bus. The configurable mesh posted transaction data bus includes a configurable command mesh and a configurable data mesh. Each of these configurable meshes includes crossbar switches and interconnecting links. A command bus transaction value issued by a processor can pass across the command mesh to an MTM. The command bus transaction bus value includes a reference value. The MTM uses the reference value to pull data across the configurable data mesh into the MTM. The MTM then uses the data to carry out the commanded transactional memory operation. Multiple such commands can pass across the posted transaction bus across different parts of the integrated circuit at the same time, and a single MTM can be carrying out multiple such operations at the same time.
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Patent Agency Ranking
公开(公告)号：US10476747B1
公开(公告)日：2019-11-12
申请号：US14923460
申请日：2015-10-27
Applicant: Netronome Systems, Inc.
Inventor： Johann H. Tönsing
IPC: H04L12/24 , H04L12/751 , H04L12/935
Abstract: A networking device includes: 1) a first processor that includes a match table, and 2) a second processor that includes both a Flow Tracking Autolearning Match Table (FTAMT) as well as a synchronized match table. A set of multiple entries stored in the synchronized match table is synchronized with a corresponding set of multiple entries in the match table on the first processor. The FTAMT, for a first packet of the flow, generates a Flow Identifier (ID) and stores the flow ID as part of a new entry for the flow. The match of a packet to one of the synchronized entries in the synchronized match table causes an action identifier to be recorded in the new entry in the FTAMT. A subsequent packet of the flow results in a hit in the FTAMT and results in the previously recorded action being applied to the subsequent packet.
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公开(公告)号：US10419406B2
公开(公告)日：2019-09-17
申请号：US15860652
申请日：2018-01-02
Applicant: Netronome Systems, Inc.
Inventor： Roelof Nico du Toit
IPC: H04L29/06
Abstract: A network device receives TCP segments of a flow via a first SSL session and transmits TCP segments via a second SSL session. Once a TCP segment has been transmitted, the TCP payload need no longer be stored on the network device. Substantial memory resources are conserved, because the device may have to handle many retransmit TCP segments at a given time. If the device receives a retransmit segment, then the device regenerates the retransmit segment to be transmitted. A data structure of entries is stored, with each entry including a decrypt state and an encrypt state for an associated SSL byte position. The device uses the decrypt state to initialize a decrypt engine, decrypts an SSL payload of the retransmit TCP segment received, uses the encrypt state to initialize an encrypt engine, re-encrypts the SSL payload, and then incorporates the re-encrypted SSL payload into the regenerated retransmit TCP segment.
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38.发明授权公开(公告)号：US10419242B1
公开(公告)日：2019-09-17
申请号：US15894866
申请日：2018-02-12
Applicant: Netronome Systems, Inc.
Inventor： Johann H. Tönsing , David George
IPC: G06F9/44 , H04L12/64 , H04L12/933 , G06F8/41 , H04L12/931
Abstract: A method involves compiling a first amount of high-level programming language code (for example, P4) and a second amount of a low-level programming language code (for example, C) thereby obtaining a first amount of native code and a second amount of native code. The high-level programming language code at least in part defines how an SDN switch performs matching in a first condition. The low-level programming language code at least in part defines how the SDN switch performs matching in a second condition. The low-level code can be a type of plugin or patch for handling special packets. The amounts of native code are loaded into the SDN switch such that a first processor (for example, x86 of the host) executes the first amount of native code and such that a second processor (for example, ME of an NFP on the NIC) executes the second amount of native code.
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公开(公告)号：US10341246B1
公开(公告)日：2019-07-02
申请号：US14530761
申请日：2014-11-02
Applicant: Netronome Systems, Inc.
Inventor： Ron Lamar Swartzentruber
IPC: G06F13/42 , H04L12/18 , H04L12/801
Abstract: A method of performing an update packet sequence number packet ready command (drop packet mode operation) is described herein. A first packet ready command is received from a memory system via a bus and onto a first network interface circuit. The first packet ready command includes a multicast value. A first communication mode is determined as a function of the multicast value. The multicast value indicates a single packet was communicated by a second network interface circuit. A packet sequence number stored in a memory unit is updated. The memory unit is included in the first network interface circuit. The first network interface circuit does not free the first packet from the memory system. The network interface circuits and the memory system are included on an Island-Based Network Flow Processor. The bus is a Command/Push/Pull (CPP) bus.
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40.发明授权公开(公告)号：US10228968B2
公开(公告)日：2019-03-12
申请号：US15688937
申请日：2017-08-29
Applicant: Netronome Systems, Inc.
Inventor： Gavin J. Stark , Rolf Neugebauer
IPC: G06F9/46 , G06F13/38 , G06F12/109 , G06F12/1081
Abstract: A Network Interface Device (NID) of a web hosting server implements multiple virtual NIDs. For each virtual NID there is a block in a memory of a transactional memory on the NID. This block stores configuration information that configures the corresponding virtual NID. The NID also has a single managing processor that monitors configuration of the plurality of virtual NIDs. If there is a write into the memory space where the configuration information for the virtual NIDs is stored, then the transactional memory detects this write and in response sends an alert to the managing processor. The size and location of the memory space in the memory for which write alerts are to be generated is programmable. The content and destination of the alert is also programmable.
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