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    SCALABLE LANGUAGE INFRASTRUCTURE FOR ELECTRONIC SYSTEM LEVEL TOOLS
    31.
    发明申请
    SCALABLE LANGUAGE INFRASTRUCTURE FOR ELECTRONIC SYSTEM LEVEL TOOLS 有权
    用于电子系统级工具的可扩展语言基础设施

    公开(公告)号：US20130024839A1

    公开(公告)日：2013-01-24

    申请号：US13356472

    申请日：2012-01-23

    Applicant: Rajesh Kumar ,  Sanjay Kumar Jain

    Inventor： Rajesh Kumar ,  Sanjay Kumar Jain

    IPC: G06F9/44

    CPC classification number: G06F8/36

    Abstract: Systems and methods of scalable language infrastructure for electronic system level tools. In accordance with embodiments of the present invention, knowledge about types, functions and the like is encapsulated in a plurality of intelligent components called active component extension modules that are external to the infrastructure. The infrastructure implements a communication mechanism between the clients and these intelligent components, and acts as a common backbone. The infrastructure itself does not maintain any knowledge about any client, types, functions, etc. In accordance with a method embodiment of the present invention, a request is received from a client of a language infrastructure. The request is forwarded from the language infrastructure to an active component extension module. The active component extension module performs a service responsive to the request.

    Abstract translation: 用于电子系统级工具的可扩展语言基础设施的系统和方法。 根据本发明的实施例，关于类型，功能等的知识被封装在被称为活动组件扩展模块的多个智能组件中，该组件在基础设施外部。 基础架构实现了客户端和这些智能组件之间的通信机制，并且作为通用骨干网。 基础设施本身并不保持关于任何客户端，类型，功能等的任何知识。根据本发明的方法实施例，从语言基础设施的客户端接收请求。 该请求从语言基础设施转发到活动组件扩展模块。 活动组件扩展模块响应于该请求执行服务。

    Stable amorphous form of carvedilol dihydrogen phosphate with stabilizer
    37.
    发明授权
    Stable amorphous form of carvedilol dihydrogen phosphate with stabilizer 有权
    卡维地洛二磷酸稳定无定形形式

    公开(公告)号：US08278461B2

    公开(公告)日：2012-10-02

    申请号：US12674642

    申请日：2008-08-06

    Applicant: Rajesh Kumar Thaper ,  Manoj Devilalji Prabhavat ,  Yogesh Dadaji Pawar ,  Pritesh R. Upadhyay

    Inventor： Rajesh Kumar Thaper ,  Manoj Devilalji Prabhavat ,  Yogesh Dadaji Pawar ,  Pritesh R. Upadhyay

    IPC: C07D209/82

    CPC classification number: C07D209/88

    Abstract: The present invention provides a novel stable amorphous form of carvedilol dihydrogen phosphate and the process for its preparation that involves reaction of carvedilol base with ortho phosphoric acid in the presence of stabilizer in a suitable solvent or mixture of solvents followed by concentration and isolation. An alternate process for preparation of amorphous form of carvedilol dihydrogen phosphate involves addition of stabiliser to the solution of stable amorphous or crystalline carvedilol dihydrogen phosphate in a suitable solvent or mixture of solvents followed by concentration and isolation. The novel stable amorphous form of carvedilol dihydrogen phosphate is highly stable.

    Abstract translation: 本发明提供了一种新颖的卡维地洛磷酸二氢不稳定形式及其制备方法，其中包括在稳定剂存在下，在合适的溶剂或溶剂混合物中将卡维地洛碱与原磷酸反应，随后浓缩和分离。 用于制备无定形形式的卡维地洛磷酸二氢盐的替代方法包括在合适的溶剂或溶剂混合物中将稳定剂加入稳定的无定形或结晶卡维地洛二磷酸盐溶液中，然后浓缩和分离。 卡维地洛磷酸二氢盐的新型稳定无定形形式是高度稳定的。

    BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE
    39.
    发明申请
    BUILT-IN SELF-TEST METHODS, CIRCUITS AND APPARATUS FOR CONCURRENT TEST OF RF MODULES WITH A DYNAMICALLY CONFIGURABLE TEST STRUCTURE 有权
    内置自测试方法，电路和装置，用于具有动态可配置的测试结构的RF模块的同时测试

    公开(公告)号：US20120191400A1

    公开(公告)日：2012-07-26

    申请号：US13042849

    申请日：2011-03-08

    Applicant: Adesh Sharadrao Sontakke ,  Rajesh Kumar Mittal ,  Rubin A. Parekhji ,  Upendra Narayan Tripathi

    Inventor： Adesh Sharadrao Sontakke ,  Rajesh Kumar Mittal ,  Rubin A. Parekhji ,  Upendra Narayan Tripathi

    IPC: G06F19/00

    CPC classification number: G01R31/31917 ,  G01R31/31716 ,  G01R31/31724

    Abstract: A testable integrated circuit chip (80, 100) includes a functional circuit (80) having modules (IP.i), a storage circuit (110) operable to hold a table representing sets of compatible tests that are compatible for concurrence, and an on-chip test controller (140, 150) coupled with said storage circuit (110) and with said functional circuit modules (IP.i), said test controller (140, 150) operable to dynamically schedule and trigger the tests in those sets, whereby promoting concurrent execution of tests in said functional circuit modules (IP.i). Other circuits, wireless chips, systems, and processes of operation and processes of manufacture are disclosed.

    Abstract translation: 可测试的集成电路芯片（80,100）包括具有模块（IP.i）的功能电路（80），存储电路（110），其可操作以保持表示兼容兼容的兼容测试集合的表，以及on 与所述存储电路（110）和所述功能电路模块（IP.i）耦合的芯片测试控制器（140,150），所述测试控制器（140,150）可操作以动态地调度和触发这些组中的测试，由此 促进在所述功能电路模块（IP.i）中并行执行测试。 公开了其他电路，无线芯片，系统以及操作过程和制造过程。

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