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    Method of production of SiC semiconductor device
    1.
    发明授权
    Method of production of SiC semiconductor device 有权
    SiC半导体器件的生产方法

    公开(公告)号：US09190482B2

    公开(公告)日：2015-11-17

    申请号：US13599010

    申请日：2012-08-30

    申请人： Katsunori Danno ,  Tsunenobu Kimoto

    发明人： Katsunori Danno ,  Tsunenobu Kimoto

    IPC分类号： H01L29/66 ,  H01L21/04

    CPC分类号： H01L29/66068 ,  H01L21/0485

    摘要： A method of production of an SiC semiconductor device, which can form an ohmic electrode while preventing electrode metal from diffusing in the SiC single crystal substrate, includes a step of forming an ohmic electrode on an SiC substrate, characterized by forming a gettering layer with a defect density higher than the SiC substrate on that substrate to be parallel with the substrate surface, then forming the ohmic electrode the gettering layer outward from the substrate.

    摘要翻译： 制造可以形成欧姆电极同时防止电极金属在SiC单晶衬底中扩散的SiC半导体器件的制造方法包括在SiC衬底上形成欧姆电极的步骤，其特征在于，形成具有 缺陷密度高于该衬底上的SiC衬底以与衬底表面平行，然后从衬底向外形成欧姆电极吸气层。

    Lateral junction field effect transistor and method of manufacturing the same
    3.
    发明授权
    Lateral junction field effect transistor and method of manufacturing the same 有权
    横向场效应晶体管及其制造方法

    公开(公告)号：US07420232B2

    公开(公告)日：2008-09-02

    申请号：US11402701

    申请日：2006-04-11

    申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    IPC分类号： H01L29/80 ,  H01L31/112

    CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

    摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

    摘要翻译： 横向结型场效应晶体管包括布置在源/漏区域之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

    Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate
    4.
    发明授权
    Method for manufacturing semiconductor device having trench in silicon carbide semiconductor substrate 有权
    一种在碳化硅半导体衬底中制造具有沟槽的半导体器件的方法

    公开(公告)号：US07241694B2

    公开(公告)日：2007-07-10

    申请号：US11105587

    申请日：2005-04-14

    申请人： Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    发明人： Yuuichi Takeuchi ,  Rajesh Kumar Malhan ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    IPC分类号： H01L21/18 ,  H01L21/302 ,  H01L21/308

    CPC分类号： H01L29/045 ,  H01L29/66068 ,  H01L29/7828 ,  H01L29/8083

    摘要： A method for manufacturing a silicon carbide semiconductor device includes the steps of: forming a trench mask on an upper surface of a semiconductor substrate; forming the trench such that the trench having an aspect ratio equal to or larger than 2 and having a trench slanting angle equal to or larger than 80 degrees is formed; and removing a damage portion in such a manner that the damage portion disposed on an inner surface of the trench formed in the semiconductor substrate in the step of forming the trench is etched and removed in hydrogen atmosphere under decompression pressure at a temperature equal to or higher than 1600° C.

    摘要翻译： 一种制造碳化硅半导体器件的方法包括以下步骤：在半导体衬底的上表面上形成沟槽掩模; 形成沟槽，使得形成具有等于或大于2并且具有等于或大于80度的沟槽倾斜角的纵横比的沟槽; 并且以这样的方式去除损伤部分，即在形成沟槽的步骤中形成在半导体衬底的沟槽的内表面上的损伤部分在氢气气氛中在等于或等于更高的温度的减压下被蚀刻和去除 比1600℃

    Lateral junction field-effect transistor
    5.
    发明申请
    Lateral junction field-effect transistor 有权
    侧面场效应晶体管

    公开(公告)号：US20060118813A1

    公开(公告)日：2006-06-08

    申请号：US11337143

    申请日：2006-01-20

    申请人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    发明人： Shin Harada ,  Kenichi Hirotsu ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

    IPC分类号： H01L31/111

    CPC分类号： H01L29/808 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/1608

    摘要： A lateral JFET has a basic structure including an n-type semiconductor layer (3) formed of an n-type impurity region and a p-type semiconductor layer formed of a p-type impurity region on the n-type semiconductor layer (3). Moreover, in the p-type semiconductor layer, there are provided a p+-type gate region layer (7) extending into the n-type semiconductor layer (3) and containing p-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3) and an n+-type drain region layer (9) spaced from the p+-type gate region layer (7) by a predetermined distance and containing n-type impurities of an impurity concentration higher than that of the n-type semiconductor layer (3). With this structure, the lateral JFET can be provided that has an ON resistance further decreased while maintaining a high breakdown voltage performance.

    摘要翻译： 横向JFET具有包括由n型杂质区形成的n型半导体层（3）和在n型半导体层（3）上由p型杂质区形成的p型半导体层的基本结构， 。 此外，在p型半导体层中，设置延伸到n型半导体层（3）中并含有杂质的p型杂质的p +型栅极区域层（7） 浓度高于n型半导体层（3）的浓度以及与p + +型栅极区域层间隔开的n + + +型漏极区域（9） （7）预定距离并且包含杂质浓度高于n型半导体层（3）的杂质浓度的n型杂质。 利用这种结构，可以提供横向JFET，其具有进一步降低的导通电阻，同时保持高的击穿电压性能。

    SiC wafer, SiC semiconductor device, and production method of SiC wafer
    6.
    发明授权
    SiC wafer, SiC semiconductor device, and production method of SiC wafer 有权
    SiC晶片，SiC半导体器件和SiC晶片的制造方法

    公开(公告)号：US06734461B1

    公开(公告)日：2004-05-11

    申请号：US10070472

    申请日：2002-03-07

    申请人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

    发明人： Hiromu Shiomi ,  Tsunenobu Kimoto ,  Hiroyuki Matsunami

    IPC分类号： H01L310312

    CPC分类号： H01L29/1608 ,  C30B23/00 ,  C30B23/02 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02516 ,  H01L21/02529 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/0262 ,  H01L21/02658 ,  H01L29/045 ,  H01L29/78

    摘要： A SiC wafer comprises a 4H polytype SiC substrate 2 in which the crystal plane orientation is substantially {03-38}, and a buffer layer 4 composed of SiC formed over this SiC substrate 2. The {03-38} plane forms an angle of approximately 35° with respect to the axial direction in which micropipes and so forth extend, so micropipes and so forth are eliminated at the crystal sides, and do not go through to an active layer 6 on the buffer layer 4. Lattice mismatching between the SiC substrate 2 and the active layer 6 is suppressed by the buffer layer 4. Furthermore, anisotropy in the electron mobility is low because a 4H polytype is used. Therefore, it is possible to obtain a SiC wafer and a SiC semiconductor device with which there is little anisotropy in the electron mobility, and strain caused by lattice mismatching can be lessened, as well as a method for manufacturing these.

    摘要翻译： SiC晶片包括其中晶体取向基本上为{03-38}的4H多型SiC衬底2，以及由该SiC衬底2上形成的由SiC构成的缓冲层4. {03-38}面形成 相对于其中微孔等的<0001>轴向延伸大约35°，因此在晶体侧消除了微管等，并且不会穿过缓冲层4上的有源层6。晶格不匹配 在SiC衬底2和有源层6之间被缓冲层4抑制。此外，由于使用4H多型，电子迁移率的各向异性低。 因此，可以获得在电子迁移率中几何异向性小的SiC晶片和SiC半导体器件，并且可以减小由晶格失配引起的应变以及其制造方法。