利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

25 条记录 (耗时 0.032 秒)

    Semiconductor device having a groove with a curved part formed on its side surface
    3.
    发明授权
    Semiconductor device having a groove with a curved part formed on its side surface 失效
    半导体器件具有在其侧表面上形成有弯曲部分的凹槽

    公开(公告)号：US5698880A

    公开(公告)日：1997-12-16

    申请号：US539380

    申请日：1995-10-05

    申请人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

    发明人： Shigeki Takahashi ,  Mitsuhiro Kataoka ,  Tsuyoshi Yamamoto ,  Yuuichi Takeuchi ,  Norihito Tokura

    IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： Y02E10/50

    摘要： A manufacturing method for a semiconductor device, which can attain a low ion voltage in a manufacturing method for a semiconductor device involving a process for forming a groove by etching prior to selective oxidation, selectively oxidizing a region including the groove and thereby making a channel part of the groove, is disclosed. A groove part is thermally oxidized by using a silicon nitride film as a mask. A LOCOS oxide film is formed by this thermal oxidation, and concurrently a U-groove is formed on the surface of an n.sup.- -type epitaxial layer eroded by the LOCOS oxide film, and the shape of the U-groove is fixed. A curve part formed during a chemical dry etching process remains as a curve part on the side surface of the U-groove. Then, an n.sup.+ -type source layer is formed by means of thermal diffusion to a junction thickness of 0.5 to 1 .mu.m, and a channel is set up as well. The junction depth obtained by this thermal diffusion is set up more deeply than the curve part which is formed during the above etching and remains on the side surface of the U-groove after the above selective thermal oxidation.

    摘要翻译： 一种用于半导体器件的制造方法的半导体器件的制造方法，其包括在选择性氧化之前通过蚀刻形成沟槽的工艺的半导体器件的制造方法，选择性地氧化包括沟槽的区域，从而形成沟道部分 的凹槽。 通过使用氮化硅膜作为掩模将槽部热氧化。 通过该热氧化形成LOCOS氧化物膜，并且在由LOCOS氧化物膜侵蚀的n型外延层的表面上形成U形槽，并且U形槽的形状被固定。 在化学干蚀刻过程中形成的曲线部分在U形槽的侧表面上保持为曲线部分。 然后，通过热扩散形成0.5±1μm的结合厚度的n +型源极层，并且还设置沟道。 通过该热扩散获得的结深度比在上述蚀刻期间形成的曲线部分更深地设置，并且在上述选择性热氧化之后保留在U形槽的侧表面上。

    Gate wiring layout for silicon-carbide-based junction field effect transistor
    4.
    发明授权
    Gate wiring layout for silicon-carbide-based junction field effect transistor 有权
    基于碳化硅的结型场效应晶体管的栅极布线布局

    公开(公告)号：US07164154B2

    公开(公告)日：2007-01-16

    申请号：US10995566

    申请日：2004-11-24

    申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

    发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

    IPC分类号： H01L29/15

    CPC分类号： H01L29/8083 ,  H01L29/1608

    摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

    摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

    Silicon carbide semiconductor device
    5.
    发明授权
    Silicon carbide semiconductor device 有权
    碳化硅半导体器件

    公开(公告)号：US07821013B2

    公开(公告)日：2010-10-26

    申请号：US11501777

    申请日：2006-08-10

    申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

    发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Rashid Jeremy ,  Andrei Mihaila ,  Florin Udrea

    IPC分类号： H01L29/12 ,  H01L29/41

    CPC分类号： H01L29/8083 ,  H01L29/1608

    摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

    摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

    Silicon carbide semiconductor device
    6.
    发明申请
    Silicon carbide semiconductor device 有权
    碳化硅半导体器件

    公开(公告)号：US20050145852A1

    公开(公告)日：2005-07-07

    申请号：US10995566

    申请日：2004-11-24

    申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

    发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

    IPC分类号： H01L29/80 ,  H01L21/337 ,  H01L29/24 ,  H01L29/808 ,  H01L29/15

    CPC分类号： H01L29/8083 ,  H01L29/1608

    摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

    摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

    Silicon carbide semiconductor device
    7.
    发明授权
    Silicon carbide semiconductor device 有权
    碳化硅半导体器件

    公开(公告)号：US06573534B1

    公开(公告)日：2003-06-03

    申请号：US09265582

    申请日：1999-03-10

    申请人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

    发明人： Rajesh Kumar ,  Tsuyoshi Yamamoto ,  Shoichi Onda ,  Mitsuhiro Kataoka ,  Kunihiko Hara ,  Eiichi Okuno ,  Jun Kojima

    IPC分类号： H01L310312

    CPC分类号： H01L29/7828 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/7838 ,  Y10S438/931

    摘要： A semiconductor device, comprising: a semiconductor substrate comprising silicon carbide of a first conductivity type; a silicon carbide epitaxial layer of the first conductivity type; a first semiconductor region formed on the semiconductor substrate and comprising silicon carbide of a second conductivity type; a second semiconductor region formed on the first semiconductor region, comprising silicon carbide of the first conductivity type and separated from the semiconductor substrate of the first conductivity type by the first semiconductor region; a third semiconductor region formed on the semiconductor region, connected to the semiconductor substrate and the second semiconductor region, comprising silicon carbide of the first conductivity type, and of higher resistance than the semiconductor substrate; and a gate electrode formed on the third semiconductor region via an insulating layer; wherein the third semiconductor layer is depleted when no voltage is being applied to the gate electrode so that said semiconductor device has a normally OFF characteristic.

    摘要翻译： 一种半导体器件，包括：包含第一导电类型的碳化硅的半导体衬底; 第一导电类型的碳化硅外延层; 形成在所述半导体衬底上并且包括第二导电类型的碳化硅的第一半导体区域; 形成在所述第一半导体区域上的第二半导体区域，包括所述第一导电类型的碳化硅并且通过所述第一半导体区域与所述第一导电类型的半导体衬底分离; 形成在所述半导体区域上的第三半导体区域，与所述半导体衬底和所述第二半导体区域连接，所述第二半导体区域包括所述第一导电型的碳化硅，并且具有比所述半导体衬底更高的电阻; 以及经由绝缘层形成在所述第三半导体区域上的栅电极; 其中当没有电压施加到所述栅电极时，所述第三半导体层被耗尽，使得所述半导体器件具有正常OFF特性。

    Semiconductor device
    8.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US6054752A

    公开(公告)日：2000-04-25

    申请号：US107507

    申请日：1998-06-30

    申请人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

    发明人： Kazukuni Hara ,  Yuichi Takeuchi ,  Tsuyoshi Yamamoto ,  Rajesh Kumar ,  Mitsuhiro Kataoka

    IPC分类号： H01L21/04 ,  H01L29/06 ,  H01L29/24 ,  H01L29/78 ,  H01L29/34 ,  H01L29/40

    CPC分类号： H01L29/7813 ,  H01L29/0611 ,  H01L29/0638 ,  H01L29/66068 ,  H01L29/7802 ,  H01L29/1608

    摘要： A semiconductor device comprises a semiconductor substrate including a first conductivity type first semiconductor layer and a second conductivity type second semiconductor layer formed on the first semiconductor layer. A unit cell for controlling current flowing between a source electrode and a drain electrode is formed in the semiconductor substrate. A trench is formed in a peripheral region of the unit cell to form mesa structure. A field relaxing layer is formed between an insulating film on a side face of the second trench and both the first semiconductor layer and the second semiconductor layer in order to relax concentration of an electric field in the insulating film.

    摘要翻译： 半导体器件包括：半导体衬底，包括形成在第一半导体层上的第一导电型第一半导体层和第二导电型第二半导体层。 在半导体衬底中形成用于控制在源电极和漏电极之间流动的电流的单元。 在单电池的周边区域形成沟槽，形成台面结构。 在第二沟槽的侧面上的绝缘膜与第一半导体层和第二半导体层之间形成场弛豫层，以使绝缘膜中的电场的集中化。

    Silicon carbide semiconductor device
    9.
    发明申请
    Silicon carbide semiconductor device 有权
    碳化硅半导体器件

    公开(公告)号：US20060284217A1

    公开(公告)日：2006-12-21

    申请号：US11501777

    申请日：2006-08-10

    申请人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

    发明人： Rajesh Kumar ,  Yuichi Takeuchi ,  Mitsuhiro Kataoka ,  Suhail Jeremy ,  Andrei Mihaila ,  Florin Udrea

    IPC分类号： H01L29/80

    CPC分类号： H01L29/8083 ,  H01L29/1608

    摘要： A silicon carbide semiconductor device includes: a semiconductor substrate including first and second gate layers, a channel layer, a source layer, and a trench; a gate wiring having a first portion and a plurality of second portions; and a source wiring having a third portion and a plurality of fourth portions. The trench extends in a predetermined extending direction. The first portion connects to the first gate layer in the trench, and extends to the extending direction. The second portions protrude perpendicularly to be a comb shape. The third portion extends to the extending direction. The fourth portions protrude perpendicularly to be a comb shape, and electrically connect to the source layer. Each of the second portions connects to the second gate layer through a contact hole.

    摘要翻译： 碳化硅半导体器件包括：包括第一和第二栅极层，沟道层，源极层和沟槽的半导体衬底; 栅极布线，具有第一部分和多个第二部分; 以及具有第三部分和多个第四部分的源极布线。 沟槽沿预定的延伸方向延伸。 第一部分连接到沟槽中的第一栅极层，并延伸到延伸方向。 第二部分垂直突出成为梳形。 第三部分延伸到延伸方向。 第四部分垂直突出成梳状，并且电连接到源层。 每个第二部分通过接触孔连接到第二栅极层。

    Semiconductor device with reduced breakdown voltage between the gate electrode and semiconductor surface
    10.
    发明授权
    Semiconductor device with reduced breakdown voltage between the gate electrode and semiconductor surface 失效
    在栅电极和半导体表面之间具有高击穿电压的半导体器件

    公开(公告)号：US5747851A

    公开(公告)日：1998-05-05

    申请号：US723804

    申请日：1996-09-30

    申请人： Yutaka Tomatsu ,  Mitsuhiro Kataoka

    发明人： Yutaka Tomatsu ,  Mitsuhiro Kataoka

    IPC分类号： H01L21/316 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

    CPC分类号： H01L29/0696 ,  H01L29/7397 ,  H01L29/7813

    摘要： A concave type DMOS transistor structure can attain improvement in a life-time of a gate insulating film. An initial groove portion is thermally oxidized with a silicon nitride film as a mask. A LOCOS oxide film is formed by this oxidation; concurrently, a U-groove is formed due to the erosion of the surface of an epitaxial layer by the LOCOS oxide film, and moreover the configuration of the groove is fixed. At this time, an inlet corner portion of the initial groove formed by chemical dry etching remains as a curving portion at a sidewall surface of the groove. Thereafter, a gate insulating film is formed, but thickness of the gate insulating film is controlled to be thicker on a groove inlet-portion side than on a groove bottom-portion side, with the curving portion as the boundary.

    摘要翻译： 凹型DMOS晶体管结构可以在栅绝缘膜的使用寿命内得到改善。 初始槽部用氮化硅膜作为掩模进行热氧化。 通过氧化形成LOCOS氧化膜; 同时，由于通过LOCOS氧化膜对外延层的表面的侵蚀，形成U形槽，此外，槽的结构是固定的。 此时，通过化学干蚀刻形成的初始凹槽的入口角部分在凹槽的侧壁表面保持为弯曲部分。 此后，形成栅极绝缘膜，但是栅极绝缘膜的厚度在凹槽入口部分侧比凹槽底部侧更厚，其中弯曲部分作为边界。