公开(公告)号：US06990619B1

公开(公告)日：2006-01-24

申请号：US09800841

申请日：2001-03-06

Applicant: Rohit Kapur ,  Thomas Williams

Inventor： Rohit Kapur ,  Thomas Williams

IPC: G01R31/28

CPC classification number: G01R31/318547

Abstract: A system for automatically retargeting test vectors for application on tester systems having different performance capabilities is provided. The system includes a user selectable mode selector that can be adjustable between different performance modes, e.g. high, medium, and low. In high performance mode, the system allows test vectors to be applied using a high performance test system, e.g. a tester having high pin count. In low performance mode, the same test vectors can be applied but using a low performance test system, e.g. a tester having low pin count. By allowing the same test vectors to be used in a high performance or a low performance test environment, a testing facility can make maximum use of its available testing equipment for efficiently testing a device.

Abstract translation: 提供了一种用于自动重定向测试向量的系统，用于具有不同性能能力的测试仪系统上的应用。 该系统包括用户可选择的模式选择器，其可以在不同的演奏模式之间调节，例如， 高，中，低。 在高性能模式下，系统允许使用高性能测试系统（例如， 具有高引脚数的测试仪。 在低性能模式中，可以应用相同的测试向量，但是使用低性能测试系统，例如， 具有低引脚数的测试仪。 通过允许在高性能或低性能测试环境中使用相同的测试向量，测试设备可以最大限度地利用其可用的测试设备来有效测试设备。

公开(公告)号：US06631344B1

公开(公告)日：2003-10-07

申请号：US09277570

申请日：1999-03-26

Applicant: Rohit Kapur ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Thomas W. Williams

IPC: G06F945

CPC classification number: G06F11/263

Abstract: In a computer implemented synthesis system, a method of generating a test pattern for use in testing device with ATE (automated test equipment). The computer implemented steps of receiving a netlist specification representing a design to be realized in physical form and storing the netlist specification in a computer memory unit, and simulating the netlist using the computer implemented synthesis system. Using the simulation instantiated within the synthesis system, deterministic test pattern generation is performed to obtain a first portion (partial) of a test pattern. The test pattern is operable to detect a fault in the circuit netlist once speculative test pattern generation is performed to obtain a remaining portion of the test pattern. The first portion and the remaining portion of the test pattern comprise a test vector operable to detect the fault when used with automated test equipment for testing a device resulting from the design.

Abstract translation: 在计算机实现的合成系统中，生成用于具有ATE（自动测试设备）的测试装置的测试图案的方法。 计算机实现了接收表示要以物理形式实现的设计的网表规范的步骤，并将网表规范存储在计算机存储单元中，以及使用计算机实现的合成系统来模拟网表。 使用在合成系统中实例化的仿真，执行确定性测试图案生成以获得测试图案的第一部分（部分）。 一旦进行推测性测试图案生成以获得测试图案的剩余部分，测试图案可操作来检测电路网表中的故障。 测试图案的第一部分和剩余部分包括一个测试矢量，用于在与自动化测试设备一起使用时检测故障，用于测试由设计产生的设备。

公开(公告)号：US06385750B1

公开(公告)日：2002-05-07

申请号：US09387865

申请日：1999-09-01

Applicant: Rohit Kapur ,  Thomas W. Williams ,  John Waicukauski ,  Peter Wohl

Inventor： Rohit Kapur ,  Thomas W. Williams ,  John Waicukauski ,  Peter Wohl

IPC: G06F1100

CPC classification number: G01R31/31813

Abstract: A method and system for improving the fault coverage of test vectors for testing integrated circuits. The present invention also provides a method and system for reducing the number of deterministic test vectors required for testing integrated circuits by inserting test points in a cost effective manner. According to an embodiment of the present invention, a fault list having all the potential faults of an integrated circuit design is initialized and all the potential faults are marked as untestable. A set of test patterns, T, for testing several of the potential faults are generated. A fault simulation process is then performed on the integrated circuit design with the test patterns, T, to mark off untested faults. During fault simulation, fault propagation is monitored to determine the nets in the design to which faults were propagated. The nets at which fault propagation discontinues (e.g., de-sensitized) are also monitored. This information is collected over the set of test patterns, T. Based on the fault propagation information, test points are selectively inserted to maximize the fault coverage of the set of test patterns, T. In one embodiment, the nets to which most untested faults propagate are selected for test point insertion. The number of test points selected may be determined by user-defined parameters. These steps are then repeated for another set of set patterns until the desired fault coverage is achieved. By adding test points, the fault coverage of the test patterns is significantly improved, thus reducing the test data volume.

Abstract translation: 一种改进测试矢量故障覆盖的方法和系统，用于测试集成电路。 本发明还提供了一种通过以成本有效的方式插入测试点来减少测试集成电路所需的确定性测试向量的数量的方法和系统。 根据本发明的实施例，初始化具有集成电路设计的所有潜在故障的故障列表，并将所有潜在故障标记为不可测。 产生一组用于测试几个潜在故障的测试模式T。 然后利用测试图案T对集成电路设计进行故障模拟处理，以标记未测试的故障。 在故障模拟期间，监控故障传播，以确定传播故障的设计网络。 还监测故障传播中断的网络（例如，去敏化）。 该信息是通过一组测试模式T收集的。根据故障传播信息，选择性地插入测试点，以最大化测试模式集合T的故障覆盖。在一个实施例中，最未经测试的故障的网络 选择传播以进行测试点插入。 所选择的测试点的数量可以由用户定义的参数确定。 然后对另一组设置模式重复这些步骤，直到实现所需的故障覆盖。 通过添加测试点，测试模式的故障覆盖率显着提高，从而降低测试数据量。

公开(公告)号：US20140032156A1

公开(公告)日：2014-01-30

申请号：US13561918

申请日：2012-07-30

Applicant: Alodeep Sanyal ,  Girish A. Patankar ,  Rohit Kapur ,  Salvatore Talluto

Inventor： Alodeep Sanyal ,  Girish A. Patankar ,  Rohit Kapur ,  Salvatore Talluto

IPC: G01R31/00 ,  G06F19/00

CPC classification number: G01R31/318371

Abstract: Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.

Abstract translation: 描述了生成用于检测集成电路（IC）中的故障的测试模式的方法和装置。 在操作期间，系统接收到IC的网表和布局。 然后，系统产生与网表相关联的一组故障，以模拟与IC相关联的一组缺陷。 接下来，系统至少基于与该组故障中的每个故障相关联的布局的一部分来确定该组故障的一组似然性。 该系统随后生成一组测试模式以对准该组故障，其中，至少基于与该组故障相关联的发生可能性的集合来生成测试模式集合。

公开(公告)号：US08584073B2

公开(公告)日：2013-11-12

申请号：US12248710

申请日：2008-10-09

Applicant: Rohit Kapur ,  Jyotirmoy Saikia ,  Rajesh Uppuluri ,  Pramod Notiyath ,  Tammy Fernandes ,  Santosh Kulkarni ,  Ashok Anbalan

Inventor： Rohit Kapur ,  Jyotirmoy Saikia ,  Rajesh Uppuluri ,  Pramod Notiyath ,  Tammy Fernandes ,  Santosh Kulkarni ,  Ashok Anbalan

IPC: G06F11/22 ,  G06F17/50

CPC classification number: G01R31/318544 ,  G01R31/318583

Abstract: Roughly described, a scan-based test architecture is optimized in dependence upon the circuit design under consideration. In one embodiment, a plurality of candidate test designs are developed. For each, a plurality of test vectors are generated in dependence upon the circuit design and the candidate test design, preferably using the same ATPG algorithm that will be used downstream to generate the final test vectors for the production integrated circuit device. A test protocol quality measure such as fault coverage is determined for each of the candidate test designs, and one of the candidate test designs is selected for implementation in an integrated circuit device in dependence upon a comparison of such test protocol quality measures. Preferably, only a sampling of the full set of test vectors that ATPG could generate, is used to determine the number of potential faults that would be found by each particular candidate test design.

公开(公告)号：US20110258498A1

公开(公告)日：2011-10-20

申请号：US12762048

申请日：2010-04-16

Applicant: Anshuman Chandra ,  Jyotirmoy Saikia ,  Rohit Kapur

Inventor： Anshuman Chandra ,  Jyotirmoy Saikia ,  Rohit Kapur

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318536 ,  G01R31/318547

Abstract: A test architecture is described that adds minimal area overhead and increases encoding bandwidth by using one or more cyclical cache chains for a set of the test patterns provided to the scan chains of the design. A multiplexer associated with a scan chain can be used to bypass a segment of the scan chain that includes unknown values. Blocking circuitry can be programmed to completely block one or more scan chains including unknown values.

Abstract translation: 描述了一种测试架构，通过为设计的扫描链提供的一组测试图案使用一个或多个循环高速缓存链来增加最小面积开销并增加编码带宽。 与扫描链相关联的多路复用器可用于绕过包括未知值的扫描链段。 阻塞电路可以编程为完全阻止一个或多个扫描链，包括未知值。

公开(公告)号：US07900105B2

公开(公告)日：2011-03-01

申请号：US12779018

申请日：2010-05-12

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic J. Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/28

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。

公开(公告)号：US20100192030A1

公开(公告)日：2010-07-29

申请号：US12362284

申请日：2009-01-29

Applicant: Rohit Kapur ,  Anshuman Chandra ,  Yasunari Kanzawa ,  Jyotirmoy Saikia

Inventor： Rohit Kapur ,  Anshuman Chandra ,  Yasunari Kanzawa ,  Jyotirmoy Saikia

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318547

Abstract: Embodiments of the present invention provide methods and apparatuses for implementing hierarchical design-for-test (DFT) logic on a circuit. The hierarchical DFT logic implements DFT circuitry that can be dedicated to a module, and which can configure DFT circuitry for multiple modules to share a sequential input signal and/or to share a sequential output signal. During operation, the DFT circuitry for a first module can propagate a bit sequence from the sequential input signal to the DFT circuitry of a second module, such that the bit sequence can include a set of control signal values for controlling the DFT circuitry, and can include compressed test vectors for testing the modules. Furthermore, the DFT circuitry for the second module can generate a sequential response signal, which combines the compressed response vectors from the second module and a sequential response signal from the DFT circuitry of the first module.

Abstract translation: 本发明的实施例提供了用于在电路上实现分层设计测试（DFT）逻辑的方法和装置。 分层DFT逻辑实现可以专用于模块的DFT电路，并且其可以配置用于多个模块的DFT电路以共享顺序输入信号和/或共享顺序输出信号。 在操作期间，用于第一模块的DFT电路可以将比特序列从顺序输入信号传播到第二模块的DFT电路，使得比特序列可以包括用于控制DFT电路的一组控制信号值，并且可以 包括测试模块的压缩测试向量。 此外，用于第二模块的DFT电路可以产生顺序响应信号，其结合来自第二模块的压缩响应向量和来自第一模块的DFT电路的顺序响应信号。

公开(公告)号：US07669098B2

公开(公告)日：2010-02-23

申请号：US11635155

申请日：2006-12-07

Applicant: Rohit Kapur ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Thomas W. Williams

IPC: G01R31/28

CPC classification number: G01R31/318572

Abstract: An embodiment provides a system for testing a circuit. During operation, the system scans-in input values into a first set of flip-flops. The outputs of the first set of flip-flops are coupled with the inputs of a circuit under test, the outputs of the circuit are coupled with the inputs of a set of multiplexers, and the outputs of the set of multiplexers are coupled with the inputs of a second set of flip-flops. Next, the system configures the set of multiplexers using a segment-selection circuit, which causes the outputs of the circuit to be coupled with the inputs of the second set of flip-flops. The system then captures the circuit's output values using the second set of flip-flops. Next, the system scans-out the circuit's output values using the second set of flip-flops. Finally, the system determines whether the chip has a fault using the output values.

Abstract translation: 实施例提供了一种用于测试电路的系统。 在操作期间，系统将输入值扫描到第一组触发器中。 第一组触发器的输出与待测电路的输入耦合，电路的输出与一组多路复用器的输入耦合，并且多路复用器组的输出与输入端耦合 的第二组触发器。 接下来，系统使用段选择电路配置多路复用器组，其使得电路的输出与第二组触发器的输入耦合。 系统然后使用第二组触发器捕获电路的输出值。 接下来，系统使用第二组触发器扫描电路的输出值。 最后，系统使用输出值确定芯片是否有故障。

公开(公告)号：US20100031101A1

公开(公告)日：2010-02-04

申请号：US12539538

申请日：2009-08-11

Applicant: Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

Inventor： Rohit Kapur ,  Nodari Sitchinava ,  Samitha Samaranayake ,  Emil Gizdarski ,  Frederic Neuveux ,  Suryanarayana Duggirala ,  Thomas W. Williams

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318572 ,  G01R31/318536

Abstract: A low overhead dynamically reconfigurable shared scan-in test architecture is provided. This test architecture advantageously allows for changing scan inputs during the scan operation on a per shift basis. The flexibility of reconfiguring the scan input to scan chain mapping every shift cycle can advantageously reduce both test data volume and test application time.

Abstract translation: 提供了低开销动态可重配置的共享扫描测试架构。 该测试架构有利地允许在每次移动的扫描操作期间改变扫描输入。 重新配置扫描输入到每个移位周期扫描链映射的灵活性可以有利地减少测试数据量和测试应用时间。