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公开(公告)号：US20250038669A1
公开(公告)日：2025-01-30
申请号：US18777716
申请日：2024-07-19
Applicant: ROHM CO., LTD.
Inventor： Yukihiro WATANABE
IPC: H02M3/158
Abstract: The present disclosure provides a semiconductor device, including: a synchronous input terminal; a synchronous output terminal; a functional circuit, having a reference clock signal generating circuit operable to generate a reference clock signal; a signal output circuit, connected to the synchronous output terminal; and a mode setting circuit, for setting an operation mode of the functional circuit and the signal output circuit to a first mode or a second mode through a mode determination process. The functional circuit is operable to perform a predetermined functional operation in synchronization with the reference clock signal in the first mode, and perform the functional operation in synchronization with an input clock signal transmitted to the synchronous input terminal from another semiconductor device in the second mode. The signal output circuit is operable to output a clock signal based on the reference clock signal from the synchronous output terminal in the first mode.
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公开(公告)号：US20250038516A1
公开(公告)日：2025-01-30
申请号：US18360538
申请日：2023-07-27
Applicant: Rohm Co., Ltd.
Inventor： Mitchell G. Van Ochten
Abstract: Systems and methods relating to battery disconnect units are disclosed. An example integrated circuit includes a first transistor operable for coupling to a first end of a coil of a DC contactor via a first pin, a second transistor operable for coupling to a second end of the coil of the DC contractor via a second pin, a third pin operable to receive an enable signal, wherein the second transistor is operable to be activated based on the enable signal and a timer operable to be activated based on the enable signal. The integrated circuit also includes circuitry operable to: in response to activating the second transistor, increase average current in the coil of the DC contactor to a first target level; in response to the timer indicating that a predetermined amount of time has elapsed, adjust the average current in the coil to a second target level, wherein the second target level is lower than the first target level; maintain an average current in the coil at the second target level until a disable signal is received via the third pin; and deactivate the second transistor in response to receiving the disable signal.
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公开(公告)号：US12211839B2
公开(公告)日：2025-01-28
申请号：US18391678
申请日：2023-12-21
Applicant: ROHM CO., LTD.
Inventor： Hirotaka Otake
IPC: H01L27/085 , H01L21/76 , H01L21/8252 , H01L29/06 , H01L29/20 , H01L29/205 , H01L29/66 , H01L29/778
Abstract: The present invention provides a nitride semiconductor device, including: a silicon substrate; a first lateral transistor over a first region of the silicon substrate and including: a first nitride semiconductor layer formed over the silicon substrate; and a first gate electrode, a first source electrode and a first drain electrode formed over the first nitride semiconductor layer; a second lateral transistor over a second region of the silicon substrate and including: a second nitride semiconductor layer formed over the silicon substrate; and a second gate electrode, a second source electrode and a second drain electrode formed over the second nitride semiconductor layer; a first separation trench formed over a third region; a source/substrate connecting via hole formed over the third region; a first interlayer insulating layer formed over the first source electrode and the second source electrode; and a second interlayer insulating layer formed in the first separation trench.
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公开(公告)号：US20250022920A1
公开(公告)日：2025-01-16
申请号：US18901248
申请日：2024-09-30
Applicant: ROHM CO., LTD.
Inventor： Keisuke NAGAYA , Yuki NAKANO , Kenji YAMAMOTO , Seigo MORI
IPC: H01L29/16 , H01L29/08 , H01L29/423 , H01L29/78
Abstract: An SiC semiconductor device includes a chip that includes an SiC monocrystal and has a main surface, a trench structure that has a side wall and a bottom wall and is formed in the main surface, and a contact region of a first conductivity type that includes a first region formed in a region along the side wall in a surface layer portion of the main surface and a second region formed in a region along the bottom wall inside the chip and having an impurity concentration lower than an impurity concentration of the first region.
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公开(公告)号：US20250022796A1
公开(公告)日：2025-01-16
申请号：US18900908
申请日：2024-09-30
Applicant: ROHM CO., LTD.
Inventor： Seigo MORI , Yuki NAKANO , Keigo MINODE
IPC: H01L23/522 , H01L27/088 , H01L29/16 , H01L29/423 , H01L29/78
Abstract: A semiconductor device includes a chip having a main surface, a trench resistance structure formed in the main surface, a gate pad that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the trench resistance structure, and a gate wiring line that has a resistance value lower than that of the trench resistance structure and that is arranged on the trench resistance structure so as to be electrically connected to the gate pad via the trench resistance structure.
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Patent Agency Ranking
公开(公告)号：US20250021128A1
公开(公告)日：2025-01-16
申请号：US18766786
申请日：2024-07-09
Applicant: ROHM CO., LTD.
Inventor： Keno SATO
Abstract: A sine wave generation circuit includes: a first direct digital synthesizer generating a digital sine wave fundamental signal having a frequency f0 in a normal operation mode and a calibration mode; a second direct digital synthesizer generating a digital second harmonic correction signal having a frequency 2f0 in the normal operation mode; a correction circuit superimposing the digital second harmonic correction signal on the digital sine wave fundamental signal; a D/A converter converting an output of the correction circuit into an analog sine wave signal; an output buffer receiving the analog sine wave signal and outputting an analog sine wave output signal; an A/D converter converting the analog sine wave output signal into a digital signal in the calibration mode; and a processing circuit generating a spectrum based on the digital signal in the calibration mode and setting a parameter of the second direct digital synthesizer based on the spectrum.
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公开(公告)号：US12199136B2
公开(公告)日：2025-01-14
申请号：US17772024
申请日：2020-09-30
Applicant: ROHM CO., LTD.
Inventor： Bungo Tanaka
Abstract: A semiconductor device includes a semiconductor chip that has a main surface, an insulating layer that is formed on the main surface, a functional device that is formed in at least one among the semiconductor chip and the insulating layer, a low potential terminal that is formed on the insulating layer and is electrically connected to the functional device, a high potential terminal that is formed on the insulating layer at an interval from the low potential terminal and is electrically connected to the functional device, and a seal conductor that is embedded as a wall in the insulating layer such as to demarcate a region including the functional device, the low potential terminal and the high potential terminal from another region in plan view, and is electrically separated from the semiconductor chip, the functional device, the low potential terminal and the high potential terminal.
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公开(公告)号：US20250015799A1
公开(公告)日：2025-01-09
申请号：US18887499
申请日：2024-09-17
Applicant: ROHM CO., LTD.
Inventor： Yasuhito SUGIMOTO
IPC: H03K17/687 , G06F11/07 , G11C7/10
Abstract: A control circuit provided in a semiconductor device receives an input data signal during a selection period in which a selection signal has a predetermined level in synchronization with a clock signal and performs a corresponding operation corresponding to the input data signal during the selection period or after the selection period. The control circuit holds an error flag indicating whether a specific error has occurred, outputs, during a part of the selection period, a response signal corresponding to the input data signal from a data output terminal and outputs, during another part of the selection period, an error flag signal corresponding to the value of the error flag from the data output terminal.
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公开(公告)号：US20250015798A1
公开(公告)日：2025-01-09
申请号：US18762898
申请日：2024-07-03
Applicant: ROHM CO., LTD.
Inventor： Hisashi SUGIE
IPC: H03K17/687 , H02P27/00
Abstract: A turn-on circuit is configured to supply a current as a source to the gate of a high-side transistor. A first current source supplies an output current that is switchable between a first current amount and a second current amount that is smaller than the first current amount. A first switch is coupled between a first output node of a first current mirror circuit and the gate of the high-side transistor. A second current source generates a second current. A second switch is coupled between a first output node of a second current mirror circuit and the gate of the high-side transistor.
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公开(公告)号：US20250015202A1
公开(公告)日：2025-01-09
申请号：US18895017
申请日：2024-09-24
Applicant: ROHM CO., LTD.
Inventor： Mitsuhide KORI
IPC: H01L29/872 , H01L29/49 , H01L29/66
Abstract: A semiconductor device includes a chip having a principal surface, a pn-junction portion extending in a horizontal direction along the principal surface inside the chip, a trench insulating structure formed in the principal surface such that the trench insulating structure penetrates through the pn-junction portion, and demarcating a diode region in the chip, a barrier forming region formed in a surface layer portion of the principal surface in the diode region, and a metal layer located on the principal surface such that the metal layer covers the barrier forming region in the diode region, and forming a Schottky-junction portion with the barrier forming region.
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