公开(公告)号：US20230411508A1

公开(公告)日：2023-12-21

申请号：US18451863

申请日：2023-08-18

Applicant: ROHM CO., LTD.

Inventor： Kenji YAMAMOTO ,  Tetsuya FUJIWARA ,  Minoru AKUTSU ,  Ken NAKAHARA ,  Norikazu ITO

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/417 ,  H01L21/265 ,  H01L21/311 ,  H01L29/51

CPC classification number: H01L29/7787 ,  H01L29/42368 ,  H01L29/4236 ,  H01L21/76 ,  H01L29/66242 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/78 ,  H01L21/02255 ,  H01L21/30621 ,  H01L21/28264 ,  H01L29/41758 ,  H01L29/66522 ,  H01L21/02241 ,  H01L21/0228 ,  H01L21/02694 ,  H01L21/2654 ,  H01L21/26586 ,  H01L21/31116 ,  H01L29/41725 ,  H01L29/51 ,  H01L29/513 ,  H01L29/2003

Abstract: A nitride semiconductor device includes an electron transit layer that is formed of a nitride semiconductor, an electron supply layer that is formed on the electron transit layer, and formed of a nitride semiconductor and that has a recess which reaches the electron transit layer from a surface, a thermal oxide film that is formed on the surface of the electron transit layer exposed within the recess, a gate insulating film that is embedded within the recess so as to be in contact with the thermal oxide film, a gate electrode that is formed on the gate insulating film and that is opposite to the electron transit layer across the thermal oxide film and the gate insulating film, and a source electrode and a drain electrode that are provided on the electron supply layer at an interval such that the gate electrode intervenes therebetween.

公开(公告)号：US20220336598A1

公开(公告)日：2022-10-20

申请号：US17639528

申请日：2020-09-25

Applicant: ROHM CO., LTD.

Inventor： Takaaki YAMANAKA ,  Yuki NAKANO ,  Kenji YAMAMOTO

IPC: H01L29/417 ,  H01L23/367 ,  H01L23/31 ,  H01L29/16 ,  H01L29/47 ,  H01L29/872 ,  H01L21/04 ,  H01L29/66

Abstract: A semiconductor device includes a chip, an electrode that is formed on the chip, an inorganic insulating layer that covers the electrode and has a first opening exposing the electrode, an organic insulating layer that covers the inorganic insulating layer, has a second opening surrounding the first opening at an interval from the first opening, and exposes an inner peripheral edge of the inorganic insulating layer in a region between the first opening and the second opening, and an Ni plating layer that covers the electrode inside the first opening and covers the inner peripheral edge of the inorganic insulating layer inside the second opening.

公开(公告)号：US20210217886A1

公开(公告)日：2021-07-15

申请号：US17212619

申请日：2021-03-25

Applicant: ROHM CO., LTD.

Inventor： Kenji YAMAMOTO ,  Tetsuya FUJIWARA ,  Minoru AKUTSU ,  Ken NAKAHARA ,  Norikazu ITO

IPC: H01L29/778 ,  H01L29/423 ,  H01L21/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/417 ,  H01L21/265 ,  H01L21/311 ,  H01L29/51

Abstract: A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

公开(公告)号：US20250040211A1

公开(公告)日：2025-01-30

申请号：US18918028

申请日：2024-10-16

Applicant: ROHM CO., LTD.

Inventor： Yuki NAKANO ,  Kenji YAMAMOTO ,  Seigo MORI

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/417 ,  H01L29/423

Abstract: An SiC semiconductor device includes an SiC semiconductor layer of a first conductivity type having a main surface, a source trench formed in the main surface and having a side wall and a bottom wall, a source electrode embedded in the source trench and having a side wall contact portion in contact with a region of the side wall of the source trench at an opening side of the source trench, a body region of a second conductivity type formed in a region of a surface layer portion of the main surface along the source trench, and a source region of the first conductivity type electrically connected to the side wall contact portion of the source electrode in a surface layer portion of the body region.

公开(公告)号：US20240120384A1

公开(公告)日：2024-04-11

申请号：US18267109

申请日：2021-11-18

Applicant: ROHM CO., LTD.

Inventor： Kenji YAMAMOTO ,  Yuki NAKANO

IPC: H01L29/10 ,  H01L29/16 ,  H01L29/36

CPC classification number: H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/872

Abstract: An SiC semiconductor device includes an SiC chip that has a main surface, and an n-type drift region that is formed in a surface layer portion of the main surface and has an impurity concentration adjusted by at least two types of pentavalent elements.

公开(公告)号：US20230197786A1

公开(公告)日：2023-06-22

申请号：US17921993

申请日：2021-07-16

Applicant: ROHM CO., LTD.

Inventor： Seigo MORI ,  Kenji YAMAMOTO ,  Hiroaki SHIRAGA ,  Yuki NAKANO ,  Keigo MINODE

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/16 ,  H01L29/417 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0869 ,  H01L21/0465 ,  H01L21/0475 ,  H01L29/063 ,  H01L29/1608 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/41741 ,  H01L29/66068

Abstract: A SiC semiconductor device includes a SiC chip having a main surface, a trench gate structure formed at the main surface, a trench source structure formed at the main surface away from the trench gate structure in one direction, an insulating film covering the trench gate structure and the trench source structure above the main surface, a gate main surface electrode formed on the insulating film and a gate wiring that is led out from the gate main surface electrode onto the insulating film such as to cross the trench gate structure and the trench source structure in the one direction, and that is electrically connected to the trench gate structure through the insulating film, and that faces the trench source structure with the insulating film between the trench source structure and the gate wiring.

公开(公告)号：US20250022916A1

公开(公告)日：2025-01-16

申请号：US18900918

申请日：2024-09-30

Applicant: ROHM CO., LTD.

Inventor： Keisuke NAGAYA ,  Yuki NAKANO ,  Kenji YAMAMOTO ,  Seigo MORI

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/04 ,  H01L29/16 ,  H01L29/739 ,  H01L29/78

Abstract: An SiC semiconductor device comprises: a chip that includes an SiC monocrystal and has a main surface; a trench structure that has a first side wall extending in an a-axis direction of the SiC monocrystal and a second side wall extending in an m-axis direction of the SiC monocrystal and is formed in the main surface; and a contact region of a first conductivity type that is formed in a region inside the chip along the trench structure at an interval in the m-axis direction from the first side wall.

公开(公告)号：US20210305363A1

公开(公告)日：2021-09-30

申请号：US17349256

申请日：2021-06-16

Applicant: ROHM CO., LTD.

Inventor： Minoru NAKAGAWA ,  Yuki NAKANO ,  Masatoshi AKETA ,  Masaya UENO ,  Seigo MORI ,  Kenji YAMAMOTO

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

公开(公告)号：US20250022920A1

公开(公告)日：2025-01-16

申请号：US18901248

申请日：2024-09-30

Applicant: ROHM CO., LTD.

Inventor： Keisuke NAGAYA ,  Yuki NAKANO ,  Kenji YAMAMOTO ,  Seigo MORI

IPC: H01L29/16 ,  H01L29/08 ,  H01L29/423 ,  H01L29/78

Abstract: An SiC semiconductor device includes a chip that includes an SiC monocrystal and has a main surface, a trench structure that has a side wall and a bottom wall and is formed in the main surface, and a contact region of a first conductivity type that includes a first region formed in a region along the side wall in a surface layer portion of the main surface and a second region formed in a region along the bottom wall inside the chip and having an impurity concentration lower than an impurity concentration of the first region.

公开(公告)号：US20230187504A1

公开(公告)日：2023-06-15

申请号：US17920024

申请日：2021-07-16

Applicant: ROHM CO., LTD.

Inventor： Kenji YAMAMOTO ,  Seigo MORI ,  Hiroaki SHIRAGA ,  Yuki NAKANO ,  Masaya UENO

IPC: H01L29/16 ,  H01L29/78 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L29/1608 ,  H01L29/7813 ,  H01L29/4236 ,  H01L29/0696 ,  H01L29/4238

Abstract: A SiC semiconductor device includes a SiC chip having a main surface that includes a first surface, a second surface hollowed in a thickness direction outside the first surface, and a connecting surface connecting the first surface and the second surface, and in which a mesa is defined by the first surface, the second surface and the connecting surface, a trench structure formed at the first surface such as to be exposed from the connecting surface, and a sidewall wiring that is formed on the second surface such as to cover the connecting surface and that is electrically connected to the trench structure.