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    Apparatus and method for scheduling threads in multi-threading processors
    32.
    发明授权
    Apparatus and method for scheduling threads in multi-threading processors 有权
    用于在多线程处理器中调度线程的装置和方法

    公开(公告)号：US08205204B2

    公开(公告)日：2012-06-19

    申请号：US12359113

    申请日：2009-01-23

    Applicant: Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

    Inventor： Ken Shoemaker ,  Sailesh Kottapalli ,  Kin-Kee Sit

    IPC: G06F9/46 ,  G06F15/00

    CPC classification number: G06F9/3802 ,  G06F9/3851 ,  G06F9/3885

    Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.

    Abstract translation: 提供多线程处理器。 多线程处理器包括接收第一线程的第一指令获取单元和用于接收第二线程的第二指令获取单元。 耦合到指令提取单元和执行单元的多线程调度器。 多线程调度器确定执行单元的宽度，并且执行单元相应地执行线程。

    SCATTER/GATHER ACCESSING MULTIPLE CACHE LINES IN A SINGLE CACHE PORT
    33.
    发明申请
    SCATTER/GATHER ACCESSING MULTIPLE CACHE LINES IN A SINGLE CACHE PORT 审中-公开
    散热器/ GATHER在单个缓存端口中访问多条缓存线

    公开(公告)号：US20120144089A1

    公开(公告)日：2012-06-07

    申请号：US13250223

    申请日：2011-09-30

    Applicant: Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

    Inventor： Jonathan C. Hall ,  Sailesh Kottapalli ,  Andrew T. Forsyth

    IPC: G06F12/08

    CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/345 ,  G06F12/06 ,  G06F12/08

    Abstract: Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.

    Abstract translation: 公开了用于访问用于散射/收集操作的多条数据高速缓存行的方法和装置。 设备的实施例可以包括地址生成逻辑，用于从具有第一值的一组对应的掩码元素中的每一个的索引集合的索引生成地址。 线或库匹配排序逻辑匹配相同高速缓存行或不同库中的地址，并且订购访问序列以允许多个高速缓存行和不同存储体中的一组地址。 地址选择逻辑将地址组指向高速缓存中的对应的不同存储体，以访问与单个访问周期中的地址组对应的多个高速缓存行中的数据元素。 拆卸/重组缓冲器根据其各自的存储体/寄存器位置对数据元素进行排序，并且收集/散布有限状态机将相应的掩模元素的值从第一值改变为第二值。

    Synchronizing multiple threads efficiently
    34.
    发明授权
    Synchronizing multiple threads efficiently 有权
    有效地同步多个线程

    公开(公告)号：US07937709B2

    公开(公告)日：2011-05-03

    申请号：US11026207

    申请日：2004-12-29

    Applicant: Sailesh Kottapalli ,  John H. Crawford

    Inventor： Sailesh Kottapalli ,  John H. Crawford

    IPC: G06F9/46 ,  G06F9/44

    CPC classification number: G06F9/522 ,  G06F9/52 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0857

    Abstract: In one embodiment, the present invention includes a method of assigning a location within a shared variable for each of multiple threads and writing a value to a corresponding location to indicate that the corresponding thread has reached a barrier. In such manner, when all the threads have reached the barrier, synchronization is established. In some embodiments, the shared variable may be stored in a cache accessible by the multiple threads. Other embodiments are described and claimed.

    Abstract translation: 在一个实施例中，本发明包括为多个线程中的每个线程分配共享变量内的位置并将值写入相应位置以指示相应线程已经达到屏障的方法。 以这种方式，当所有线程都到达障碍物时，建立同步。 在一些实施例中，共享变量可以存储在可由多个线程访问的高速缓存中。 描述和要求保护其他实施例。

    TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT
    35.
    发明申请
    TRANSACTION BASED SHARED DATA OPERATIONS IN A MULTIPROCESSOR ENVIRONMENT 有权
    在多处理器环境中基于交易的共享数据操作

    公开(公告)号：US20110055493A1

    公开(公告)日：2011-03-03

    申请号：US12943314

    申请日：2010-11-10

    Applicant: Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

    Inventor： Sailesh Kottapalli ,  John H. Crawford ,  Kushagra Vaid

    IPC: G06F12/14

    CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

    Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

    Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

    Transaction based shared data operations in a multiprocessor environment
    38.
    发明申请
    Transaction based shared data operations in a multiprocessor environment 有权
    多处理器环境中基于事务的共享数据操作

    公开(公告)号：US20060161740A1

    公开(公告)日：2006-07-20

    申请号：US11027623

    申请日：2004-12-29

    Applicant: Sailesh Kottapalli ,  John Crawford ,  Kushagra Vaid

    Inventor： Sailesh Kottapalli ,  John Crawford ,  Kushagra Vaid

    IPC: G06F13/00

    CPC classification number: G06F9/528 ,  G06F9/3834 ,  G06F9/544

    Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are track by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

    Abstract translation: 本文描述的装置和方法用于通过事务执行来处理利用无锁同步的多个处理器之间的共享存储器访问。 在软件中划分的事务被推测执行。 在执行期间，无效远程访问/请求到从共享存储器加载并被写入到共享存储器的地址由事务缓冲器跟踪。 如果遇到无效访问，则重新执行该事务。 在重新执行事务的预定次数之后，可以非推测地用锁/信号量重新执行事务。

    Pipelined look-up in a content addressable memory
    39.
    发明申请
    Pipelined look-up in a content addressable memory 审中-公开
    流水线查找内容可寻址内存

    公开(公告)号：US20060143374A1

    公开(公告)日：2006-06-29

    申请号：US11027636

    申请日：2004-12-29

    Applicant: Sailesh Kottapalli ,  Udo Walterscheidt ,  Michael Reitsma

    Inventor： Sailesh Kottapalli ,  Udo Walterscheidt ,  Michael Reitsma

    IPC: G06F12/00

    CPC classification number: G11C15/00 ,  G06F12/1027 ,  Y02D10/13

    Abstract: A pipelined look-up in a content addressable memory disclosed. In one embodiment, a content addressable memory includes a first cell and a second cell. The first cell is to compare a first bit of look-up data to a first bit of stored data. The second cell is to compare a second bit of look-up data to a second bit of stored data, and to generate a signal to disable the first cell if the second bit of look-up data does not match the second bit of stored data.

    Abstract translation: 公开了在内容可寻址存储器中的流水线查找。 在一个实施例中，内容可寻址存储器包括第一单元和第二单元。 第一个单元是将查找数据的第一位与存储数据的第一位进行比较。 第二单元是将第二位查找数据与存储数据的第二位进行比较，并且如果第二位查找数据与存储数据的第二位不匹配，则产生禁止第一单元的信号 。

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