公开(公告)号：US20060187606A1

公开(公告)日：2006-08-24

申请号：US11407986

申请日：2006-04-21

Applicant: Siavash Fallahi ,  Kevin Brown

Inventor： Siavash Fallahi ,  Kevin Brown

IPC: H02H1/00

CPC classification number: H04M1/2535 ,  H03H7/06 ,  H03H7/075 ,  H03H7/38 ,  H04M11/066

Abstract: An internet protocol telephone includes a substrate having an input and an output that are capable of being connected to the internet protocol (IP) network. A relay is disposed on the substrate and is connected between the input and the output of the substrate. The relay includes first and second native FETs that have a threshold voltage of approximately zero volts. Therefore, the relay is nominally turned-on, even when little or no voltage (or power) is applied to the IP telephone substrate, as during the discovery mode of IP telephone operation. During discovery mode, The IP phone is configured to be responsive to extended link pulses and block data packets that are associated with legacy devices. Data packets have a higher signal duration and are more continuous than extended link pulses. The IP phone includes a switchable ground that is connected to the gates of the native devices, and is controlled by a rectifier and filter circuit that are connected to the substrate input. If the IP phone receives legacy data packets during discovery mode, then the high signal duration and continuous nature of the data packets are sufficient to cause the rectifier to generate a rectified signal having sufficient amplitude to activate the switchable ground, so as to ground the gates of the native devices and therefore turn-off the native devices. Therefore, the data packets are rejected and are not passed back to the switch. Extended link pulses have a frequency that is too low to generate a rectified signal that is sufficient to activate the switchable ground, and therefore the native devices remain turned-on. Accordingly, the extended link pulses are passed back to the switch.

公开(公告)号：US06958648B2

公开(公告)日：2005-10-25

申请号：US10928371

申请日：2004-08-30

Applicant: Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

Inventor： Felix Cheung ,  Kevin T. Chan ,  Siavash Fallahi

IPC: H03G1/00 ,  H03F1/36

CPC classification number: H03G1/0088

Abstract: A programable gain amplifier (PGA) has an amplifier and a variable resistor that is connected to the output of the amplifier. The variable resistor includes a resistor that is connected to a reference voltage and multiple parallel taps that tap off the resistor. A two-stage switch network having fine stage switches and coarse stage switches connects the resistor taps to an output node of the PGA. The taps and corresponding fine stage switches are arranged into two or more groups, where each group has n-number of fine stage switches and corresponding taps. One terminal of each fine stage switch is connected to the corresponding resistor tap, and the other terminal is connected to an output terminal for the corresponding group. The coarse stage switches select from among the groups of fine stage switches, and connect to the output of the PGA. During operation, one selected tap is connected to the output of the PGA by closing the appropriate fine stage switch and coarse stage switch, where the selected tap defines a selected group of the fine stage switches. Additionally, one fine stage switch is closed in each of the non-selected groups of fine stage switches. In one embodiment, the location of the closed switches in the non-selected groups is the mirror image of the location in an adjacent group. This reduces the transient voltages that occur when tap selection changes from one group to another.

Abstract translation: 可编程增益放大器（PGA）具有放大器和连接到放大器的输出的可变电阻器。 可变电阻器包括连接到参考电压的电阻器和分离电阻器的多个并联抽头。 具有精细级开关和粗级开关的两级开关网络将电阻抽头连接到PGA的输出节点。 抽头和相应的精细级开关被布置成两组或更多组，其中每组具有n个细级开关和相应的抽头。 每个精细级开关的一个端子连接到相应的电阻抽头，另一个端子连接到相应组的输出端子。 粗级开关从精细级开关组中选择，并连接到PGA的输出。 在运行期间，一个选择的分接头通过关闭适当的细级开关和粗级开关连接到PGA的输出，其中所选择的分接头定义了选定的精细级开关组。 此外，每个非选择的精细级开关组中的一个精细级开关闭合。 在一个实施例中，未选择组中的闭合开关的位置是相邻组中位置的镜像。 这样可以减少轻敲选择从一个组变为另一组时发生的瞬态电压。

公开(公告)号：US06930519B2

公开(公告)日：2005-08-16

申请号：US10782890

申请日：2004-02-23

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K23/68 ,  H03L7/081 ,  H03L7/099 ,  H03L7/18 ,  H03K23/00

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a Phase Lock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过任何非整数输出信号频率相对于锁相环（PLL）的参考信号频率进行倍频/除法，同时保持低抖动。 在一个实施例中，本发明将可用时钟相位的数目增加到M，然后每K / M周期将输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US06922109B2

公开(公告)日：2005-07-26

申请号：US10131034

申请日：2002-04-25

Applicant: Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

Inventor： Siavash Fallahi ,  Chun Ying Chen ,  Mark J. Chambers

IPC: G11B20/14 ,  H03L7/089 ,  H03L7/099 ,  H03L7/18 ,  H03L7/00

CPC classification number: H03L7/18 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/099 ,  H03L7/0996 ,  H03L7/0998

Abstract: A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

Abstract translation: 一种用于产生具有用于接收参考信号的输入端的多个合成时钟的系统，耦合到所述输入信号端的锁相环电路，其中所述锁相环电路能够产生频率锁定到所述输入信号的多个输出信号 参考信号并且具有多个不同的相位，耦合到锁相环电路的相位旋转器，其中相位旋转器产生更大的多个相位。

公开(公告)号：US06714056B2

公开(公告)日：2004-03-30

申请号：US10227259

申请日：2002-08-26

Applicant: Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

Inventor： Siavash Fallahi ,  Myles Wakayama ,  Pieter Vorenkamp

IPC: H03K2300

CPC classification number: H03L7/081 ,  H03K23/68 ,  H03L7/0996 ,  H03L7/18

Abstract: A method and system described for producing frequency multiplication/division by any non-integer output signal frequency relative to a reference signal frequency of a PhaseLock-Loop (PLL), while simultaneously maintaining low jitter. In one embodiment, the invention increases the number of the available clock phases to M and then shifts the output clock phase by one, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another aspect, the MUX is placed in the feedback loop of the PLL. In one embodiment, a quantizer is used to drive the MUX.

Abstract translation: 一种方法和系统，用于通过相对于锁相环（PLL）的参考信号频率的任何非整数输出信号频率产生倍频/除法，同时保持低抖动。在一个实施例中，本发明增加了 将可用的时钟相位设置为M，然后将每个K / M周期的输出时钟相位移位1。 在本发明的一个方面，这通过将多路复用器（MUX）添加到PLL的输出端来实现，以实现每K / M个周期的相移。 在另一方面，MUX被放置在PLL的反馈回路中。 在一个实施例中，使用量化器来驱动MUX。

公开(公告)号：US06608536B2

公开(公告)日：2003-08-19

申请号：US09986752

申请日：2001-11-09

Applicant: Siavash Fallahi

Inventor： Siavash Fallahi

IPC: H03H706

CPC classification number: H03H7/38 ,  H03H7/06 ,  H03H7/075 ,  H03H7/1758 ,  H03H7/425

Abstract: A constant impedance filter maintains a constant input impedance for frequencies that are both inside the filter passband and outside the filter passband. The constant input impedance appears as a pure resistance. The constant impedance filter includes a plurality of filter poles that are connected in series. Each of the filter poles include an inductor, a capacitor, and a resistor. The value of the inductor, the capacitor, and the resistor are selected to provide a constant input impedance over frequency for each pole of the filter, which produces a constant input impedance for the entire filter over frequency. The constant impedance filter can be implemented as a low pass filter, a high pass filter, or a bandpass filter. Furthermore, the constant impedance filter can be implemented in a single-ended configuration or a differential configuration.