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    FRONT SIDE BUS PERFORMANCE USING AN EARLY DEFER-REPLY MECHANISM
    32.
    发明申请
    FRONT SIDE BUS PERFORMANCE USING AN EARLY DEFER-REPLY MECHANISM 审中-公开
    前端总线性能使用早期的回复机制

    公开(公告)号：US20080320192A1

    公开(公告)日：2008-12-25

    申请号：US11764936

    申请日：2007-06-19

    Applicant: Sundaram CHINTHAMANI ,  Sivakumar RADHAKRISHNAN

    Inventor： Sundaram CHINTHAMANI ,  Sivakumar RADHAKRISHNAN

    IPC: G06F13/362

    CPC classification number: G06F13/161

    Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for improving the performance of a front side bus using an early defer-reply mechanism. In some embodiments, an integrated circuit receives a memory read request and accesses memory to obtain read data responsive to receiving the memory read request. The integrated circuit may initiate a defer-reply transaction corresponding to the memory read request N front side bus (FSB) clocks prior to receiving the read data from the memory.

    Abstract translation: 本发明的实施例一般涉及使用早期延迟回复机制来改善前端总线的性能的系统，方法和装置。 在一些实施例中，集成电路接收存储器读取请求并访问存储器以响应于接收到存储器读取请求而获得读取数据。 在从存储器接收到读取数据之前，集成电路可以发起对应于存储器读请求N前端总线（FSB）时钟的延迟回复事务。

    Ring interface and ring network bus flow control system
    36.
    发明授权
    Ring interface and ring network bus flow control system 有权
    环形接口和环网总线流量控制系统

    公开(公告)号：US06496516B1

    公开(公告)日：2002-12-17

    申请号：US09206697

    申请日：1998-12-07

    Applicant: Stephen Dabecki ,  Sivakumar Radhakrishnan

    Inventor： Stephen Dabecki ,  Sivakumar Radhakrishnan

    IPC: H04L1243

    CPC classification number: H04L47/30 ,  H04L12/42 ,  H04L45/40 ,  H04L47/10 ,  H04L47/50 ,  H04L47/52 ,  H04L47/527

    Abstract: A ring interface is coupled to a current node in a ring network having a plurality of nodes and corresponding ring interface for each of said nodes. The ring interface includes a ring input port operative to conduct upstream message packets from a previous node to the ring interface, a ring output port operative to conduct message packets to a next node of the ring network, and a bypass queue operative to buffer message packets. A receive queue buffers message packets before passing them on to the current node. An address filter is coupled to the ring input port to receive the upstream message packets, read their destination addresses and pass them to the bypass queue if the addresses correspond to another node and pass them to the receive queue if their addresses are that of the current node. A transmit queue buffers message packets from the current node and a bypass-transmit queue arbiter is coupled to outputs of the bypass queue and the transmit queue and is operative to select message packets from one of the bypass queue and the transmit queue in accordance with predetermined selection criterion and transmits the selected message packets to the ring output port.

    Abstract translation: 环形接口耦合到具有多个节点的环形网络中的当前节点和用于每个所述节点的相应环形接口。 所述环形接口包括环形输入端口，用于将上一个节点的上行消息包传送到所述环形接口;环形输出端口，用于对所述环形网络的下一个节点进行消息分组;以及旁路队列，用于缓冲消息分组 。 接收队列将消息包传递到当前节点之前进行缓冲。 地址过滤器被耦合到环形输入端口以接收上行消息分组，读取其目的地地址并将它们传递到旁路队列，如果地址对应于另一个节点，并将它们传递到接收队列，如果它们的地址是当前的 节点。 发送队列缓冲来自当前节点的消息分组，并且旁路发送队列仲裁器耦合到旁路队列和发送队列的输出，并且可操作以根据预定的选择从旁路队列和发送队列中的一个选择消息分组 选择标准，并将所选择的消息分组发送到环形输出端口。

    Allowed cell rate reciprocal approximation in rate-based available bit rate schedulers
    37.
    发明授权
    Allowed cell rate reciprocal approximation in rate-based available bit rate schedulers 失效
    基于速率的可用比特率调度器允许的信元速率相互近似

    公开(公告)号：US5751697A

    公开(公告)日：1998-05-12

    申请号：US568347

    申请日：1995-12-06

    Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki

    Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki

    IPC: G06F7/52 ,  G06F7/535 ,  H04L12/56 ,  H04Q11/04 ,  H04L12/24 ,  G06F1/02

    CPC classification number: G06F7/535 ,  H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5684 ,  Y10S370/905

    Abstract: A method of scheduling cell transmission over an asynchronous transfer mode communication channel. The channel has a characteristic transmission rate that is related to the system clock frequency .function. and an allowed cell rate ACR expressed as a floating point number having a mantissa m, and an exponent e, where 0.ltoreq.m.ltoreq.511, 0.ltoreq.e.ltoreq.31 and ACR=(1+m/512)*2.sup.e. If m.gtoreq.128 then the reciprocal of the mantissa portion (1+m/512) is evaluated by piece-wise linear approximation of the function: ##EQU1## Otherwise, if m

    Abstract translation: 一种通过异步传输模式通信信道调度小区传输的方法。 信道具有与系统时钟频率f相关的特征传输速率，以及表示为具有尾数m的浮点数的允许信元速率ACR和指数e，其中0≤m≤511,0 / = 128，则尾数部分的倒数（1 + m / 512）通过函数的分段线性近似来估计：否则，如果m <128，则尾数部分通过分段估计 函数的明智的线性近似：然后，调度所选择的单元在相对于所选单元之前发送的单元的传输时间T0的时间T发送，其中T = T0 +（ACR-1）* f 。 本发明的硬件实施例仅需要一个9位二进制补码器，三个11位加法器和用于多路复用/控制的胶合逻辑就可以使用符合ATM论坛流量管理标准的VLSI电路来实现，而不需要硬件划分或 乘法。

    Available bit rate scheduler
    38.
    发明授权
    Available bit rate scheduler 失效
    可用比特率调度程序

    公开(公告)号：US5706288A

    公开(公告)日：1998-01-06

    申请号：US622398

    申请日：1996-03-27

    Applicant: Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Walden Wong

    Inventor： Sivakumar Radhakrishnan ,  Stephen J. Dabecki ,  David Walden Wong

    IPC: H04L12/56 ,  H04Q11/04 ,  H04J3/22

    CPC classification number: H04Q11/0478 ,  H04L2012/5635 ,  H04L2012/5679 ,  H04L2012/568

    Abstract: An available bit rate scheduling method and apparatus for asynchronous transfer mode communication of a plurality of cells over a network characterized by a system clock frequency f and an allowed cell rate ACR. Each cell belongs to an assigned virtual circuit communication channel which is defined by a set of negotiated traffic parameters. The invention partitions the ACR's of the virtual circuits into a smaller subset of profiles/sub-profiles and conducts a deterministic search to service them. The scheduler incorporates a profile generator for iteratively generating a number p of the profiles by (i) outputting a k*modulo 2.sup.i th one of the profiles during each kth iteration of the profile generator, where 1.ltoreq.i.ltoreq.p and 1.ltoreq.k.ltoreq.p-1; (ii) outputting a null profile during each 2.sup.p th one of the iterations; and, (iii) dispatching the profiles from the profile generator to the profile queue such that a particular profile is dispatched at a time T=T.sub.0 +(1/ACR)*f, where T.sub.0 is the dispatch time of a profile dispatched immediately prior to the particular profile. A profile queue coupled to the profile generator receives and sequentially stores the generated profiles. A virtual circuit processor sequentially receives the profiles from the profile queue and, for each one of the received profiles, dispatches to an output queue all virtual circuits which are characterized by the one received profile.

    Abstract translation: 一种用于通过网络异步传输模式通信的可用比特率调度方法和装置，其特征在于系统时钟频率f和允许的小区速率ACR。 每个小区属于由一组协商的业务参数定义的分配的虚拟电路通信信道。 本发明将虚拟电路的ACR分成简档/子简档的较小子集，并进行确定性搜索以对其进行维护。 调度器包括一个简档生成器，用于通过（i）在简档生成器的每个第k次迭代期间输出ak *模2个模型之一来迭代地生成数据p，其中1 i = p和1 < / = k

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