公开(公告)号：US20100229021A1

公开(公告)日：2010-09-09

申请号：US12399736

申请日：2009-03-06

Applicant: Georgios K. Konstadinidis ,  Sudhakar Bobba

Inventor： Georgios K. Konstadinidis ,  Sudhakar Bobba

IPC: G06F1/08 ,  G06F1/28

CPC classification number: G06F1/305 ,  G06F1/08 ,  G06F1/3203

Abstract: A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

Abstract translation: 用于微处理器的电压下降监视和校正电路包括：监视器电路，被配置为监视微处理器的电压下降并执行暂时的跳时技术以补偿电压下降。 用于监视和校正微处理器的电压下降的方法包括：监视微处理器的电压下降; 并执行临时跳时技术以补偿电压下降。 计算机系统包括存储器; 可操作地连接到存储器的处理器; 以及存储在存储器中的计算机可读指令，用于使处理器：监视微处理器的电压下降; 并执行临时的时钟跳跃技术来补偿电压下降。

公开(公告)号：US06721936B2

公开(公告)日：2004-04-13

申请号：US09997435

申请日：2001-11-30

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: G06F1750

CPC classification number: H05K9/0039

Abstract: A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to assign a shield potential. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to assign a shield potential is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract translation: 提供了一种优先屏蔽信号以增加隐式去耦电容的方法。 通过使用信号处于特定值的概率来分配屏蔽电位来优先屏蔽信号。 此外，提供了通过使用信号处于特定值的概率来分配屏蔽电位来优先屏蔽信号以增加去耦电容的集成电路。 此外，提供了一种用于通过使用信号处于特定值的概率来分配屏蔽电位来优先屏蔽信号以增加去耦电容的计算机系统。 此外，提供一种具有用于优先屏蔽信号以通过使用信号处于特定值的概率来分配屏蔽电位来增加隐式解耦电容的可执行指令的计算机可读介质。 此外，提供了通过增加隐式去耦电容来提高系统性能的方法。

公开(公告)号：US06687886B2

公开(公告)日：2004-02-03

申请号：US09997864

申请日：2001-11-30

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: G06F1750

CPC classification number: G06F17/505

Abstract: A method that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Because the shield may also be used to form the power and ground grid, a balanced number of power versus ground lines is desired. A method for inverting the signal to balance the number of power versus ground lines is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract translation: 提供了优先屏蔽信号以增加去耦电容的方法。 基于信号处于特定值的概率来优先屏蔽信号。 因为屏蔽也可以用于形成电源和接地网格，所以需要平衡数量的功率对地线。 提供了一种用于反转信号以平衡功率与接地线数量的方法。 此外，提供了通过增加隐式去耦电容来提高系统性能的方法。

公开(公告)号：US06646472B1

公开(公告)日：2003-11-11

申请号：US10156249

申请日：2002-05-28

Applicant: Pradeep Trivedi ,  Sudhakar Bobba

Inventor： Pradeep Trivedi ,  Sudhakar Bobba

IPC: H03K1900

CPC classification number: G06F1/10 ,  G06F1/3203

Abstract: A technique for reducing the power consumed by a clock driver circuit involves selecting between a first power supply path and a second power supply path in response to a power reduction signal. A driver circuit drives an output clock signal from the selected one of the first power supply path and the second power supply path. By reducing the voltage on one of the first power supply path and the second power supply path, the power consumed by the clock driver circuit may be selectively reduced.

Abstract translation: 用于减少时钟驱动器电路消耗的功率的技术包括响应于功率降低信号在第一电源路径和第二电源路径之间进行选择。 驱动电路驱动来自第一电源路径和第二电源路径中选择的一个的输出时钟信号。 通过降低第一电源路径和第二电源路径中的一个电压，可以选择性地减少由时钟驱动器电路消耗的功率。

公开(公告)号：US06628138B2

公开(公告)日：2003-09-30

申请号：US09997865

申请日：2001-11-30

Applicant: Sudhakar Bobba ,  Tyler Thorp

Inventor： Sudhakar Bobba ,  Tyler Thorp

IPC: H03K1716

CPC classification number: H01L23/5223 ,  H01L23/5225 ,  H01L23/5286 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit that preferentially shields a signal to increase decoupling capacitance is provided. The signal is preferentially shielded based on a probability of the signal being at a specific value. Further, a method for increasing an amount of decoupling capacitance on a circuit through preferential shielding is provided. Further, a method to increase system performance by increasing implicit decoupling capacitance is provided.

Abstract translation: 提供了优先屏蔽信号以增加去耦电容的集成电路。 基于信号处于特定值的概率来优先屏蔽信号。 此外，提供了一种通过优先屏蔽来增加电路上的去耦电容量的方法。 此外，提供了通过增加隐式去耦电容来提高系统性能的方法。

公开(公告)号：US06617699B2

公开(公告)日：2003-09-09

申请号：US09997844

申请日：2001-11-29

Applicant: Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

Inventor： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

IPC: H01L2940

CPC classification number: H01L23/50 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107

Abstract: A 120 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 120 degree bump placement structures is provided.

Abstract translation: 提供集成电路电网的120度凸块布置布局。 这种布局提高了集成电路的性能和可靠性，并为集成电路设计人员增加了设计集成电路的灵活性和均匀性。 此外，提供了具有多个120度凸块布置结构的集成电路的顶部金属层的图案化凸块阵列。