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    Standard cell for arithmetic logic unit and chip card controller
    31.
    发明授权
    Standard cell for arithmetic logic unit and chip card controller 有权
    用于算术逻辑单元和芯片卡控制器的标准单元

    公开(公告)号：US07921148B2

    公开(公告)日：2011-04-05

    申请号：US11501305

    申请日：2006-08-09

    申请人： Thomas Kuenemund

    发明人： Thomas Kuenemund

    IPC分类号： G06F7/38

    CPC分类号： G06F7/5016 ,  G06F7/764

    摘要： A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

    摘要翻译： 用于算术逻辑单元的单元包括第一输入; 第二个输入 输入输入; 第一控制输入和第二控制输入; 以及连接到第一输入端，第二输入端，进位输入端，第一控制输入端和第二控制输入端的电路。 该电路具有第一输出和第二输出，当第一控制输入和第二控制输入的值等于进位时的值时，第二输出具有作为第一输入和第二输入的函数的第一值， 并且当第一控制输入和第二控制输入处的值与进位输入处的值无关时具有作为第一输入和第二输入的函数的第二值。

    Memory for storing a binary state
    32.
    发明授权
    Memory for storing a binary state 有权
    用于存储二进制状态的存储器

    公开(公告)号：US07898842B2

    公开(公告)日：2011-03-01

    申请号：US12106640

    申请日：2008-04-21

    申请人： Thomas Kuenemund

    发明人： Thomas Kuenemund

    IPC分类号： G11C11/00

    CPC分类号： G11C11/412 ,  G11C8/16

    摘要： A memory cell for storing a binary state, the memory cell being adapted for storing a binary state based on a write indication and a binary write masking value and for storing a complementary binary state based on the write indication and a complementary binary write masking value.

    摘要翻译： 一种用于存储二进制状态的存储器单元，所述存储器单元适于基于写入指示和二进制写入掩蔽值存储二进制状态，并且用于基于所述写入指示和互补的二进制写入掩蔽值来存储互补的二进制状态。

    Logic gate
    33.
    发明授权
    Logic gate 有权
    逻辑门

    公开(公告)号：US07830170B2

    公开(公告)日：2010-11-09

    申请号：US12346240

    申请日：2008-12-30

    申请人： Thomas Kuenemund ,  Artur Wroblewski

    发明人： Thomas Kuenemund ,  Artur Wroblewski

    IPC分类号： H03K19/096

    CPC分类号： H03K19/094 ,  H03K19/20

    摘要： A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

    摘要翻译： 逻辑门包括第一开关，第二开关，数据网络和保持电路。 第一开关适于将逻辑节点连接到响应于使能信号的转换的第一电位。 第二开关适于通过响应于使能信号的转换的电路径将逻辑节点连接到第二电位。 数据网络在电气路径内串联连接。 保持电路包括串联连接在逻辑节点和第一电位之间并可彼此独立控制的第三和第四开关，第三开关适于在逻辑节点上的电位呈现第一电位并被打开的情况下被关闭 如果逻辑节点上的电位呈现第二个电位。

    STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER
    34.
    发明申请
    STANDARD CELL FOR ARITHMETIC LOGIC UNIT AND CHIP CARD CONTROLLER 审中-公开
    用于算术逻辑单元和芯片卡控制器的标准单元

    公开(公告)号：US20100281092A1

    公开(公告)日：2010-11-04

    申请号：US12770833

    申请日：2010-04-30

    申请人： Thomas Kuenemund

    发明人： Thomas Kuenemund

    IPC分类号： G06F7/38

    CPC分类号： G06F7/5016 ,  G06F7/764

    摘要： A masked ALU cell for a certain bit position p is provided. The cell comprises a base unit operable to generate a masked inverted carry out bit co*_n and an inverted masked sum bit s*_n based on a first masked output a*, a second masked output b*, and a re-masked carry bit input ci*; a transformation unit coupled to the base unit, the transformation unit having a first masked input bit aka, a second masked input bit bkb, a first mask input bit ka, a second mask input bit kb, a third mask input bit ks, and a fourth mask input bit kp, wherein the transformation unit is operable to generate the first masked output a* based on the first masked input bit aka, the first mask input bit ka, and the fourth mask input bit kp; the second masked output b* based on the second masked input bit bkb, the second mask input bit kb, and fourth mask input bit kp; and a masked sum bit sks based on the third mask input bit ks, the inverted masked sum bit s*_n, and the fourth mask input bit kp.

    摘要翻译： 提供用于特定位位置p的屏蔽的ALU单元。 该单元包括基本单元，其可操作以基于第一屏蔽输出a *，第二屏蔽输出b *和重新屏蔽的进位位产生屏蔽的反向执行位组合和反向屏蔽和位s * _n 输入ci *; 变换单元，其耦合到所述基本单元，所述变换单元具有第一屏蔽输入位aka，第二屏蔽输入位bkb，第一掩码输入位ka，第二掩码输入位kb，第三掩码输入位ks和 第四掩模输入位kp，其中所述变换单元可操作以基于所述第一屏蔽输入位aka，所述第一掩码输入位ka和所述第四掩码输入位kp产生所述第一屏蔽输出a *; 基于第二被屏蔽输入位bkb，第二掩码输入位kb和第四掩码输入位kp的第二屏蔽输出b *; 以及基于第三掩码输入位ks，反相掩蔽和位s * _n和第四掩码输入位kp的掩蔽和位位sks。

    LOGIC GATE
    35.
    发明申请
    LOGIC GATE 有权
    逻辑门

    公开(公告)号：US20100164549A1

    公开(公告)日：2010-07-01

    申请号：US12346240

    申请日：2008-12-30

    申请人： THOMAS KUENEMUND ,  ARTUR WROBLEWSKI

    发明人： THOMAS KUENEMUND ,  ARTUR WROBLEWSKI

    IPC分类号： H03K19/20 ,  H03K19/094

    CPC分类号： H03K19/094 ,  H03K19/20

    摘要： A logic gate comprises a first switch, a second switch, a data network and a keeping circuitry. The first switch is adapted to connect a logic node to a first potential responsive to a transition of an enabling signal. The second switch is adapted to connect the logic node to a second potential via an electrical path responsive to a transition of the enabling signal. The data network is serially connected within the electrical path. The keeping circuitry comprises third and fourth switches serially connected between the logic node and the first potential and being controllable separately from each other, the third switch being adapted to be closed in case a potential on the logic node assumes the first potential and to be opened in case the potential on the logic node assumes the second potential.

    摘要翻译： 逻辑门包括第一开关，第二开关，数据网络和保持电路。 第一开关适于将逻辑节点连接到响应于使能信号的转换的第一电位。 第二开关适于通过响应于使能信号的转换的电路径将逻辑节点连接到第二电位。 数据网络在电气路径内串联连接。 保持电路包括串联连接在逻辑节点和第一电位之间并可彼此独立控制的第三和第四开关，第三开关适于在逻辑节点上的电位呈现第一电位并被打开的情况下被关闭 如果逻辑节点上的电位呈现第二个电位。

    DIGITAL FAULT DETECTION CIRCUIT AND METHOD
    36.
    发明申请
    DIGITAL FAULT DETECTION CIRCUIT AND METHOD 有权
    数字故障检测电路及方法

    公开(公告)号：US20100164507A1

    公开(公告)日：2010-07-01

    申请号：US12344771

    申请日：2008-12-29

    申请人： THOMAS KUENEMUND

    发明人： THOMAS KUENEMUND

    IPC分类号： G01R31/02

    CPC分类号： G01R31/318522 ,  G01R31/31816

    摘要： Some embodiments show a digital fault detection circuit with an input circuit comprising an input and at least one output, wherein a first signal state at the input causes a predetermined signal state at the output and a second signal state at the input leaves the output floating. Moreover the digital fault detection circuit may comprise a signal line with a signal line input and a signal line output, wherein the signal line input is coupled to the output of the input circuit and furthermore a keeper circuit coupled to the signal line output and configured to keep the signal line at the predetermined signal state, after the signal state at the input has changed from the first signal state to the second signal state. The digital fault detection circuit may further comprise at least one fault detector cell, which is coupled to the signal line between the signal line input and the signal line output and which is configured to change the state of the signal line which is otherwise kept by the keeper circuit, in response to a fault.

    摘要翻译： 一些实施例示出了具有包括输入和至少一个输出的输入电路的数字故障检测电路，其中输入处的第一信号状态在输出处引起预定的信号状态，并且输入处的第二信号状态使得输出浮动。 此外，数字故障检测电路可以包括具有信号线输入和信号线输出的信号线，其中信号线输入耦合到输入电路的输出，此外，耦合到信号线输出的保持电路被配置为 在输入信号状态从第一信号状态变为第二信号状态之后，将信号线保持在预定信号状态。 数字故障检测电路还可以包括至少一个故障检测器单元，其耦合到信号线输入和信号线输出之间的信号线，并且被配置为改变信号线的状态，否则由 保护电路，以应对故障。

    DEVICE FOR STORING A BINARY STATE
    37.
    发明申请
    DEVICE FOR STORING A BINARY STATE 有权
    存储二进制状态的设备

    公开(公告)号：US20080205169A1

    公开(公告)日：2008-08-28

    申请号：US12038393

    申请日：2008-02-27

    申请人： Thomas Kuenemund ,  Andreas Wenzel

    发明人： Thomas Kuenemund ,  Andreas Wenzel

    IPC分类号： G11C8/20

    CPC分类号： G11C17/12 ,  G11C8/20 ,  G11C17/18

    摘要： Device for storing a binary state defined by a first binary value and a second binary value complementary thereto, the device capable of being queried by a query signal so as to output, in dependence on a binary masking state, the first binary value at a first output and the second binary value at a second output or vice versa.

    摘要翻译： 用于存储由第一二进制值和与其互补的第二二进制值定义的二进制状态的设备，所述设备能够被查询信号查询，以便根据二进制掩蔽状态来输出第一二进制值 输出，第二个二进制值在第二个输出，反之亦然。

    Standard cell for arithmetic logic unit and chip card controller
    39.
    发明申请
    Standard cell for arithmetic logic unit and chip card controller 有权
    用于算术逻辑单元和芯片卡控制器的标准单元

    公开(公告)号：US20080126456A1

    公开(公告)日：2008-05-29

    申请号：US11501305

    申请日：2006-08-09

    申请人： Thomas Kuenemund

    发明人： Thomas Kuenemund

    IPC分类号： G06F7/575

    CPC分类号： G06F7/5016 ,  G06F7/764

    摘要： A cell for an arithmetic logic unit includes a first input; a second input; a carry-in input; a first control input and a second control input; and a circuit connected to the first input, the second input, the carry-in input, the first control input, and the second control input. The circuit has a first output and a second output, the second output having a first value as a function of the first input and the second input when the first control input and the second control input are supplied values equal to a value at the carry-in input, and having a second value as a function of the first input and second input when the values at the first control input and the second control input are independent of the value at the carry-in input.

    摘要翻译： 用于算术逻辑单元的单元包括第一输入; 第二个输入 输入输入; 第一控制输入和第二控制输入; 以及连接到第一输入端，第二输入端，进位输入端，第一控制输入端和第二控制输入端的电路。 该电路具有第一输出和第二输出，当第一控制输入和第二控制输入的值等于进位时的值时，第二输出具有作为第一输入和第二输入的函数的第一值， 并且当第一控制输入和第二控制输入处的值与进位输入处的值无关时具有作为第一输入和第二输入的函数的第二值。

    Transmission device
    40.
    发明授权
    Transmission device 有权
    传输设备

    公开(公告)号：US07161869B2

    公开(公告)日：2007-01-09

    申请号：US11022278

    申请日：2004-12-23

    申请人： Thomas Kuenemund

    发明人： Thomas Kuenemund

    IPC分类号： G11C8/00

    CPC分类号： G06F7/00 ,  G06F2207/7223 ,  G06F2207/7266 ,  G11C5/063

    摘要： A transmission device has a device for generating a signal pair and a device for generating a recovered data signal. The device for generating the signal pair is formed to output a first data signal either as first signal or as first complementary signal in response to a value of a switching signal. The device for generating a recovered data signal is, in turn, formed to output the first signal as a first recovered data signal or the first complementary signal as the first recovered data signal in response to a value of the switching signal.

    摘要翻译： 发送装置具有用于产生信号对的装置和用于产生恢复的数据信号的装置。 用于产生信号对的装置被形成为响应于切换信号的值，将第一数据信号作为第一信号或第一互补信号输出。 用于产生恢复的数据信号的装置又被形成为响应于切换信号的值，将作为第一恢复数据信号或第一互补信号的第一信号作为第一恢复数据信号输出。