公开(公告)号：US11895236B2

公开(公告)日：2024-02-06

申请号：US18097867

申请日：2023-01-17

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC分类号： H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

CPC分类号： H04L9/0866 ,  G06F12/0246 ,  G06F12/1408 ,  G06F12/1425 ,  G09C1/00 ,  G11C7/24 ,  G11C16/22 ,  H04L9/3278 ,  G06F2212/1052 ,  G11C7/1006 ,  G11C8/20 ,  G11C16/0425 ,  G11C16/0466 ,  H03K19/003 ,  H04L2209/12

摘要： A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US11823731B2

公开(公告)日：2023-11-21

申请号：US17448976

申请日：2021-09-27

申请人： Micron Technology, Inc.

发明人： Kenneth W. Marr ,  Michael A. Smith

IPC分类号： G11C8/20 ,  G11C11/4078 ,  G11C16/22 ,  G11C16/04 ,  G11C7/24 ,  G11C11/22 ,  G11C11/16

CPC分类号： G11C11/4078 ,  G11C7/24 ,  G11C8/20 ,  G11C11/1695 ,  G11C11/2295 ,  G11C16/0483 ,  G11C16/22

摘要： Devices are disclosed. A device may include a source configured to couple to a number of memory cells. The device may also include at least one transistor coupled between the source and a ground voltage. Further, the device may include an antifuse coupled between the at least one transistor and the ground voltage. Methods and systems are also disclosed.

公开(公告)号：US11436156B2

公开(公告)日：2022-09-06

申请号：US17158979

申请日：2021-01-26

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F12/14 ,  G11C11/16 ,  G06F9/455 ,  G11C8/20

摘要： Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

公开(公告)号：US10916280B2

公开(公告)日：2021-02-09

申请号：US15922694

申请日：2018-03-15

申请人： Dell Products, L.P.

发明人： Adolfo S. Montero ,  Mark Tracy Ellis

IPC分类号： G11C8/20 ,  G11C7/10

摘要： Systems and methods for securely sharing a memory between an Embedded Controller (EC) and a Platform Controller Hub (PCH). In some embodiments, an IHS may include: a chipset; a flash device coupled to the chipset; and an EC coupled to the flash device via a first bus and to the chipset via a second bus, wherein the EC comprises a Read-Only Memory (ROM) portion and a Random Access Memory (RAM) portion, the EC configured to: retrieve EC firmware from the flash device via the first bus; store the retrieved EC firmware in the RAM portion; and prior to the execution of any instruction stored in the RAM portion, relinquish access to the flash device via the first bus.

公开(公告)号：US10915457B2

公开(公告)日：2021-02-09

申请号：US16520292

申请日：2019-07-23

申请人： Micron Technology, Inc.

发明人： Steven Jeffrey Wallach

IPC分类号： G06F12/10 ,  G06F12/1009 ,  G06F12/14 ,  G11C11/16 ,  G06F9/455 ,  G11C8/20

摘要： Systems, apparatuses, and methods related to a computer system having a page table entry containing permission bits for predefined types of memory accesses made by executions of routines in predefined domains are described. The page table entry can be used to map a virtual memory address to a physical memory address. In response to a routine accessing the virtual memory address, a permission bit corresponding to the execution domain of the routine and a type of the memory access can be extracted from the page table entry to determine whether the memory access is to be rejected.

公开(公告)号：US10911229B2

公开(公告)日：2021-02-02

申请号：US15864445

申请日：2018-01-08

申请人： MACRONIX INTERNATIONAL CO., LTD.

发明人： Chun-Hsiung Hung ,  Chin-Hung Chang

IPC分类号： G06F11/30 ,  H04L9/08 ,  H04L9/32 ,  G06F12/14 ,  G11C7/24 ,  G09C1/00 ,  G11C16/22 ,  G06F12/02 ,  H03K19/003 ,  G11C7/10 ,  G11C8/20 ,  G11C16/04

摘要： A device which can be implemented on a single packaged integrated circuit or a multichip module comprises a plurality of non-volatile memory cells, and logic to use a physical unclonable function to produce a key and to store the key in a set of non-volatile memory cells in the plurality of non-volatile memory cells. The physical unclonable function can use entropy derived from non-volatile memory cells in the plurality of non-volatile memory cells to produce a key. Logic is described to disable changes to data in the set of non-volatile memory cells, and thereby freeze the key after it is stored in the set.

公开(公告)号：US20200227103A1

公开(公告)日：2020-07-16

申请号：US16542671

申请日：2019-08-16

申请人： eMemory Technology Inc.

发明人： Chi-Yi SHAO

IPC分类号： G11C8/20 ,  G06F12/14 ,  G11C11/4074 ,  G11C8/18 ,  G11C16/08 ,  G11C16/24

摘要： A random code generator includes a control circuit, a high voltage power supply, a memory module and a counter. The control circuit generates a control signal and an enabling signal. During a program cycle, the enabling signal is activated. The high voltage power supply receives the enabling signal. A charge pump of the high voltage power supply generates a program voltage according to an oscillation signal. When the enabling signal is activated, the high voltage power supply outputs the program voltage. The memory module determines a selected memory cell of the memory module according to the control signal. During the program cycle, the selected memory cell receives the program voltage. During the program cycle, the counter counts a pulse number of the oscillation signal to acquire a counting value, and the control circuit determines a random code according to the counting value.

公开(公告)号：US10706934B2

公开(公告)日：2020-07-07

申请号：US16510168

申请日：2019-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hidehiro Fujiwara ,  Ching-Wei Wu

IPC分类号： G06F11/00 ,  G11C16/08 ,  G11C29/02 ,  G11C8/10 ,  G11C5/02 ,  G11C5/06 ,  G11C16/10 ,  G11C16/34 ,  G11C29/14 ,  G11C29/00 ,  G11C8/08 ,  G11C8/20

摘要： A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.

公开(公告)号：US20190333555A1

公开(公告)日：2019-10-31

申请号：US16203351

申请日：2018-11-28

申请人： SK hynix Inc.

发明人： Hyuck Sang YIM ,  Ki Won LEE ,  Seoung Ju CHUNG

IPC分类号： G11C8/06 ,  G11C8/20 ,  G11C8/18 ,  G11C8/12 ,  G11C7/10

摘要： A semiconductor system includes a first set of at least one semiconductor device, and a second set of at least one semiconductor device. The semiconductor system includes a control block for receiving an external address and providing the first and second sets of semiconductor devices with an internal address. The control block provides a semiconductor device from the first set with a first internal address corresponding to the external address, and the control block provides a semiconductor device from the second set with a second internal address that does not correspond to the external address.

公开(公告)号：US20190080765A1

公开(公告)日：2019-03-14

申请号：US16160406

申请日：2018-10-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hidehiro FUJIWARA ,  Ching-Wei WU

IPC分类号： G11C16/08 ,  G11C29/02 ,  G11C5/06 ,  G11C16/10 ,  G11C16/34 ,  G11C29/14 ,  G11C8/10 ,  G11C5/02 ,  G11C29/00 ,  G11C8/20 ,  G11C8/08

CPC分类号： G11C16/08 ,  G11C5/025 ,  G11C5/063 ,  G11C8/08 ,  G11C8/10 ,  G11C8/20 ,  G11C16/105 ,  G11C16/3481 ,  G11C29/024 ,  G11C29/025 ,  G11C29/14 ,  G11C29/783

摘要： A data storage device can detect for a failure in decoding of an x-bit row address and/or a y-bit column of an (x+y)-bit address. The data storage device decodes the x-bit row address and/or the y-bit column address to provide wordlines (WLs) and/or bitlines (BLs) to access one or more cells from among a memory array of the data storage device. The data storage device compares one or more subsets of the WLs and/or of the BLs to each other to detect for the failure. The data storage device determines the failure is present in the decoding of the x-bit row address and/or the y-bit column of the (x+y)-bit address when one or more WL and/or BL from among the one or more subsets of the WLs and/or the BLs differ.