公开(公告)号：US20060154418A1

公开(公告)日：2006-07-13

申请号：US11160176

申请日：2005-06-13

Applicant: Ko-Hsing Chang ,  Tung-Po Chen ,  Tung-Ming Lai ,  Chen-Chiu Hsue

Inventor： Ko-Hsing Chang ,  Tung-Po Chen ,  Tung-Ming Lai ,  Chen-Chiu Hsue

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/7833

Abstract: A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.

Abstract translation: 描述了用于制造OTEPROM的方法。 在衬底上形成隧道氧化物层，第一导电层，第一图案化掩模层。 在衬底中形成沟槽。 形成绝缘层以填充沟槽。 目的地形成浮栅的第一导电层的一部分被暴露，然后在其上形成覆盖层。 去除第一图案化掩模层，然后在衬底上形成第二导电层和第二图案化掩模层。 使用第二图案化掩模层和盖层作为掩模形成字线和浮栅。 去除第二图案化掩模层，然后在字线和浮栅两侧以及字线和浮栅之间的衬底中形成源极/漏极区。

公开(公告)号：US06316321B1

公开(公告)日：2001-11-13

申请号：US09314527

申请日：1999-05-19

Applicant: Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

Inventor： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L29/7833

Abstract: A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

Abstract translation: 公开了一种用于形成MOSFET的方法。 该方法包括首先提供衬底，其上已经形成了没有间隔物的栅极。 在栅极的侧壁上形成第一间隔物，随后在衬底中形成轻掺杂漏极。 接下来，在第一间隔物上形成第二间隔物。 最后，在衬底中形成重掺杂漏极。 本发明可以提高门的电阻的稳定性并减少机器的污染。 因此，MOSFET的制造的质量和效率将得到提高。

公开(公告)号：US6133130A

公开(公告)日：2000-10-17

申请号：US181530

申请日：1998-10-28

Applicant: Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

Inventor： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/4763

CPC classification number: H01L27/10873 ,  H01L21/28518 ,  H01L21/823443 ,  H01L27/10894 ,  H01L29/665

Abstract: A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.

Abstract translation: 一种方法包括在嵌入式动态随机存取存储器（DRAM）的制造中的自对准硅化物（Salicide）技术。 在硅晶片上，第一MOS晶体管形成在逻辑器件区域中，第二MOS晶体管形成在存储器件区域中。 改进的方法包括在衬底上形成至少覆盖第一（第二）MOS晶体管的绝缘层。 去除绝缘层的顶部以仅露出第一（第二）栅极结构的顶部。 覆盖第一MOS晶体管的绝缘层的一部分被去除以暴露第一MOS晶体管。 使用第二MOS晶体管上的剩余绝缘层作为掩模，执行自对准硅化物制造工艺以在第一可互换源极/漏极区上形成自对准硅化物层，并且第一（第二）多晶硅栅极的暴露的顶表面 结构体。

公开(公告)号：US5970379A

公开(公告)日：1999-10-19

申请号：US678824

申请日：1996-07-12

Applicant: Tung-Po Chen ,  Hong-Tsz Pan

Inventor： Tung-Po Chen ,  Hong-Tsz Pan

IPC: H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L21/44

CPC classification number: H01L21/76805 ,  H01L21/28518 ,  H01L21/76814 ,  H01L29/665

Abstract: A method of reducing the loss of metal silicide in pre-metal etching which includes the following steps. A polysilicon gate electrode and implanted source/drain electrodes are formed on a silicon substrate. A metal silicide layer is formed on the polysilicon gate electrode and the source/drain electrodes. On the surface of the substrate, the polysilicon gate electrode, the source-drain electrodes region and the metal silicide layer, a protecting glass for insulation is formed and then dry etched to form a contact window. The metal silicide layer will form a damaged metal silicide layer in the contact window. Thereafter, a thermal process is conducted to repair the damaged metal silicide layer and finally, pre-metal etching is conducted completing the process. Pursuant to this method, the extremely low resistance of the metal silicide remains.

Abstract translation: 一种降低金属硅化物在金属前蚀刻中的损耗的方法，包括以下步骤。 在硅衬底上形成多晶硅栅电极和注入源/漏电极。 在多晶硅栅极电极和源极/漏极上形成金属硅化物层。 在基板的表面上形成多晶硅栅电极，源极 - 漏极区域和金属硅化物层，形成用于绝缘的保护玻璃，然后干法蚀刻以形成接触窗口。 金属硅化物层将在接触窗中形成损坏的金属硅化物层。 此后，进行热处理以修复损坏的金属硅化物层，最后完成该工艺的金属前蚀刻。 根据该方法，残留金属硅化物的极低电阻。