公开(公告)号：US06187674B1

公开(公告)日：2001-02-13

申请号：US09208605

申请日：1998-12-08

申请人： Tung-Po Chen ,  Yung-Chang Lin ,  Keh-Ching Huang ,  Jacob Chen

发明人： Tung-Po Chen ,  Yung-Chang Lin ,  Keh-Ching Huang ,  Jacob Chen

IPC分类号： H01L2144

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/4941

摘要： A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

摘要翻译： MOS门制造操作能够防止酸腐蚀和车站污染。 该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。 接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。 最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。 薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

公开(公告)号：US6133130A

公开(公告)日：2000-10-17

申请号：US181530

申请日：1998-10-28

申请人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

发明人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L27/10873 ,  H01L21/28518 ,  H01L21/823443 ,  H01L27/10894 ,  H01L29/665

摘要： A method includes a self-aligned silicide (Salicide) technology in fabrication of an embedded dynamic random access memory (DRAM). On a silicon wafer, a first MOS transistor is formed in a logic device region, and second MOS transistor is formed in a memory device region. The improved method includes forming an insulating layer over the substrate at least covering the first (second) MOS transistor. A top portion of the insulating layer is removed to expose only a top portion of the first (second) gate structure. A portion of the insulating layer covering the first MOS transistor is removed to expose the first MOS transistor. Using the remaining insulating layer on the second MOS transistor as a mask, the Salicide fabrication process is performed to form a self-aligned silicide layer on the first interchangeable source/drain region, and the exposed top surface of the first (second) polysilicon gate structure.

摘要翻译： 一种方法包括在嵌入式动态随机存取存储器（DRAM）的制造中的自对准硅化物（Salicide）技术。 在硅晶片上，第一MOS晶体管形成在逻辑器件区域中，第二MOS晶体管形成在存储器件区域中。 改进的方法包括在衬底上形成至少覆盖第一（第二）MOS晶体管的绝缘层。 去除绝缘层的顶部以仅露出第一（第二）栅极结构的顶部。 覆盖第一MOS晶体管的绝缘层的一部分被去除以暴露第一MOS晶体管。 使用第二MOS晶体管上的剩余绝缘层作为掩模，执行自对准硅化物制造工艺以在第一可互换源极/漏极区上形成自对准硅化物层，并且第一（第二）多晶硅栅极的暴露的顶表面 结构体。

公开(公告)号：US06225155B1

公开(公告)日：2001-05-01

申请号：US09208602

申请日：1998-12-08

申请人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

发明人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC分类号： H01L218234

CPC分类号： H01L27/10894 ,  H01L21/823814 ,  H01L21/823835 ,  H01L27/10873

摘要： In a method of forming a salicide layer in an embedded dynamic random access memory, a thin oxide layer, a silicon nitride layer and a thick oxide layer are sequentially formed over a substrate after performing an annealing process to a source/drain region. The insulating layer on a gate and a source/drain region in a logic region and a gate in a memory region. Salicide layers are formed on the three regions mentioned above. Formation of the salicide layers can lower resistance of the three regions, increase speed and can avoid forming a salicide layer on the source/drain region in the memory region. Thus, current leakage can be avoided. In addition, the step of forming a salicide layer is conducted after the annealing process of the source/drain region, so problems of thermal stability and inter-diffusion of impurities in the polysilicon layer can also be solved.

摘要翻译： 在嵌入式动态随机存取存储器中形成硅化物层的方法中，在对源极/漏极区域进行退火处理之后，在衬底上顺序地形成薄氧化物层，氮化硅层和厚氧化物层。 逻辑区域中的栅极和源极/漏极区域上的绝缘层以及存储区域中的栅极。 在上述三个区域上形成硅化物层。 自对准层的形成可以降低三个区域的电阻，提高速度，并且可以避免在存储区域的源极/漏极区域上形成自对准硅化物层。 因此，可以避免电流泄漏。 此外，在源极/漏极区域的退火处理之后进行形成硅化物层的步骤，因此也可以解决多晶硅层中的杂质的热稳定性和相互扩散问题。

公开(公告)号：US06197672B1

公开(公告)日：2001-03-06

申请号：US09208271

申请日：1998-12-08

申请人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

发明人： Yung-Chang Lin ,  Tung-Po Chen ,  Jacob Chen

IPC分类号： H01L213205

CPC分类号： H01L21/28061 ,  H01L29/4941

摘要： A method for forming a dual polycide gate. A substrate that has an isolation structure is provided, a polysilicon layer (or an &agr;-Si layer) is deposited over the substrate, N-type and P-type dopants are implanted into the polysilicon layer to form a dual gate having an N-type gate and a P-type gate. An annealing step is performed to restore the surface crystal structure of the polysilicon layer, an oxide layer is deposited on the doped polysilicon layer, and a silicide layer is formed over the oxide layer. The silicide layer, the oxide layer and the polysilicon layer are defined to form a polycide gate, a lightly doped source/drain region is formed beside the gate in the substrate. A spacer is formed on the sidewall of the gate, and a heavily doped source/drain region is formed beside the spacer in the substrate.

摘要翻译： 一种形成双重多晶硅栅极的方法。 提供具有隔离结构的衬底，在衬底上沉积多晶硅层（或α-Si层），将N型和P型掺杂剂注入到多晶硅层中以形成具有N- 型门和P型门。 执行退火步骤以恢复多晶硅层的表面晶体结构，在掺杂多晶硅层上沉积氧化物层，并且在氧化物层上形成硅化物层。 硅化物层，氧化物层和多晶硅层被定义为形成多晶硅栅极，在衬底的栅极旁边形成轻掺杂的源极/漏极区域。 在栅极的侧壁上形成间隔物，并且在衬底中的间隔物旁边形成重掺杂的源/漏区。

公开(公告)号：US06177334B1

公开(公告)日：2001-01-23

申请号：US09203024

申请日：1998-12-01

申请人： Tung-Po Chen ,  Yung-Chang Lin ,  Jacob Chen

发明人： Tung-Po Chen ,  Yung-Chang Lin ,  Jacob Chen

IPC分类号： H01L2120

CPC分类号： H01L21/02071 ,  H01L21/28061 ,  H01L21/28247 ,  H01L21/32137 ,  H01L29/6659

摘要： A manufacturing method is capable of preventing corrosion of a metal oxide semiconductor. The manufacturing method sequentially forms a polysilicon layer, a silicide layer and a top cap layer over a substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the silicide layer. Finally, the substrate is cleaned, and then of a source/drain region having a lightly doped drain structure is formed on each side of the gate.

摘要翻译： 制造方法能够防止金属氧化物半导体的腐蚀。 制造方法在衬底上顺序地形成多晶硅层，硅化物层和顶盖层，然后蚀刻以形成栅极结构。 接下来，进行快速热处理以在硅化物层的暴露的侧壁上形成氧化物层。 最后，清洗衬底，然后在栅极的每一侧形成具有轻掺杂漏极结构的源/漏区。

公开(公告)号：US06350646B1

公开(公告)日：2002-02-26

申请号：US09484786

申请日：2000-01-18

申请人： Tung-Po Chen ,  Yung-Chang Lin

发明人： Tung-Po Chen ,  Yung-Chang Lin

IPC分类号： H01L218242

CPC分类号： H01L21/76831 ,  H01L21/76802 ,  H01L27/10855 ,  H01L27/10894

摘要： A method for manufacturing a semiconductor device is disclosed. The method can reduce thermal budget in node contact application. It includes mainly the following processes. A substrate is first provided, then a dielectric layer is formed over the substrate. Next, a node contact opening through the dielectric layer to top surface of the substrate is formed by coating the dielectric layer with a photoresist layer, patterning the photoresist layer with pattern of a node contact by exposure and development, then etching the dielectric layer until top surface of said substrate exposed using said patterned photoresist layer as a mask. Subsequently, the photoresist layer is removed. Finally, a silicon nitride layer is formed on inside wall of the node contact opening by rapid thermal chemical vapor deposition (RTCVD).

摘要翻译： 公开了一种制造半导体器件的方法。 该方法可以降低节点接触应用中的热预算。 它主要包括以下过程。 首先提供衬底，然后在衬底上形成电介质层。 接下来，通过介电层到基板的顶表面的节点接触开口通过用光致抗蚀剂层涂覆介电层而形成，通过曝光和显影对具有节点接触图案的光致抗蚀剂层进行图案化，然后蚀刻介电层直到顶部 使用所述图案化的光致抗蚀剂层作为掩模曝光所述衬底的表面。 随后，去除光致抗蚀剂层。 最后，通过快速热化学气相沉积（RTCVD）在节点接触开口的内壁上形成氮化硅层。

公开(公告)号：US6150205A

公开(公告)日：2000-11-21

申请号：US227761

申请日：1999-01-08

申请人： Tung-Po Chen ,  Yung-Chang Lin

发明人： Tung-Po Chen ,  Yung-Chang Lin

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of fabricating a dual gate. A first conductive type region and a second conductive type region isolated by an isolation structure is provided. A polysilicon layer is formed on the first and the second conductive type regions. A diffusion layer containing second type conductive ions is formed on a second part of the polysilicon layer which covers the second conductive type region. First conductive ions are implanted into a part of the first conductive region which covers the first conductive type region. A first thermal process is performed. A metal layer is formed, and a second thermal process is performed, so that the metal layer is transformed into a metal silicide layer. A dielectric layer is formed on the metal layer. The dielectric layer, the metal silicide layer, diffusion layer, and the polysilicon layer are patterned to form a dual gate.

摘要翻译： 一种制造双门的方法。 提供了由隔离结构隔离的第一导电类型区域和第二导电类型区域。 在第一和第二导电类型区域上形成多晶硅层。 在覆盖第二导电类型区域的多晶硅层的第二部分上形成包含第二类型导电离子的扩散层。 第一导电离子被注入到覆盖第一导电类型区域的第一导电区域的一部分中。 执行第一热处理。 形成金属层，进行第二热处理，使金属层转变为金属硅化物层。 在金属层上形成电介质层。 将电介质层，金属硅化物层，扩散层和多晶硅层图案化以形成双栅极。

公开(公告)号：US6124621A

公开(公告)日：2000-09-26

申请号：US314528

申请日：1999-05-19

申请人： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

发明人： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

IPC分类号： H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L29/6656 ,  Y10S257/90 ,  Y10S257/915

摘要： A structure of a spacer in a semiconductor device is disclosed. Firstly, a gate without a spacer is provided on a substrate. A first insulating layer is formed on the sidewall of the gate. After a lightly doped drain is subsequently achieved in the substrate, a second insulating layer is formed on the first spacer. The process following this embodiment described above is to form a heavily doped drain in the substrate, then the whole MOSFET fabrication is completed. The present invention can enhance the stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

摘要翻译： 公开了半导体器件中的间隔物的结构。 首先，在衬底上设置没有间隔物的栅极。 第一绝缘层形成在栅极的侧壁上。 在衬底中随后实现轻掺杂漏极之后，在第一间隔物上形成第二绝缘层。 按照上述实施例描述的工艺是在衬底中形成重掺杂漏极，然后完成整个MOSFET制造。 本发明可以提高门的电阻的稳定性并减少机器的污染。 因此，MOSFET的制造的质量和效率将得到提高。

公开(公告)号：US06316321B1

公开(公告)日：2001-11-13

申请号：US09314527

申请日：1999-05-19

申请人： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

发明人： Yung-Chang Lin ,  Jih-Wen Chou ,  Tung-Po Chen

IPC分类号： H01L21336

CPC分类号： H01L29/6659 ,  H01L21/28061 ,  H01L29/4941 ,  H01L29/6656 ,  H01L29/7833

摘要： A method for forming MOSFET is disclosed. The method includes firstly providing a substrate, on which a gate without spacer is already formed. A first spacer is formed on sidewall of the gate, a lightly doped drain is subsequently formed in the substrate. Next, a second spacer is formed on the first spacer. Finally, a heavily doped drain is formed in the substrate. The present invention can enhance stability of resistance of the gate and reduce pollution of the machine. Therefore, quality and efficiency of the fabrication of MOSFET will be enhanced.

摘要翻译： 公开了一种用于形成MOSFET的方法。 该方法包括首先提供衬底，其上已经形成了没有间隔物的栅极。 在栅极的侧壁上形成第一间隔物，随后在衬底中形成轻掺杂漏极。 接下来，在第一间隔物上形成第二间隔物。 最后，在衬底中形成重掺杂漏极。 本发明可以提高门的电阻的稳定性并减少机器的污染。 因此，MOSFET的制造的质量和效率将得到提高。

公开(公告)号：US06200848B1

公开(公告)日：2001-03-13

申请号：US09208612

申请日：1998-12-08

申请人： Yung-Chang Lin ,  Jacob Chen

发明人： Yung-Chang Lin ,  Jacob Chen

IPC分类号： H01L218242

CPC分类号： H01L27/10888 ,  H01L27/10894

摘要： A method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. Metal oxide semiconductors and source/drain regions are respectively formed in the memory region and in the logic region. A defined dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region until the source/drain regions are exposed. Silicide layers are formed over the contact holes. Portions of the silicide layer extend to surface of the dielectric layer neighboring the contact holes. A defined inter-layer dielectric layer is formed over the substrate. Vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. The self-aligned contact is formed.

摘要翻译： 一种制造自对准接触的方法。 衬底被定义为存储区域和逻辑区域。 金属氧化物半导体和源极/漏极区域分别形成在存储区域和逻辑区域中。 在衬底上形成限定的电介质层。 接触孔分别形成在存储区域和逻辑区域中，直到源极/漏极区域露出。 硅化物层形成在接触孔上。 硅化物层的一部分延伸到与接触孔相邻的电介质层的表面。 在衬底上形成限定的层间电介质层。 通孔分别形成在存储器区域和逻辑区域中。 通孔填充有导电层。 形成自对准接触。