公开(公告)号：US07273787B2

公开(公告)日：2007-09-25

申请号：US11164332

申请日：2005-11-18

Applicant: Wen-Ji Chen ,  Tung-Po Chen ,  Kai-An Hsueh ,  Sheng-Hone Zheng

Inventor： Wen-Ji Chen ,  Tung-Po Chen ,  Kai-An Hsueh ,  Sheng-Hone Zheng

IPC: H01L21/8234

CPC classification number: H01L27/105 ,  H01L21/76229 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/11546 ,  Y10S438/981

Abstract: A method for manufacturing a gate dielectric layer is provided. A substrate divided into at least a high voltage circuit region and a low voltage circuit region is provided. A first dielectric layer serving as gate dielectric layer in the high voltage circuit region is formed on the substrate. A mask layer is formed over the first dielectric layer. The mask layer, the first dielectric layer and the substrate are patterned to form trenches in the substrate. An isolation layer is formed to fill the trenches. The mask layer and part of the isolation layer are removed to expose the surface of the first dielectric layer. The first dielectric layer of the low voltage circuit region is removed to expose the surface of the substrate. A second dielectric layer having a thickness smaller than the first dielectric layer is formed on the substrate in the low voltage circuit region.

Abstract translation: 提供一种用于制造栅介质层的方法。 提供了分成至少高压电路区域和低电压电路区域的衬底。 在基板上形成用作高电压电路区域中的栅极电介质层的第一介质层。 在第一电介质层上形成掩模层。 将掩模层，第一介电层和衬底图案化以在衬底中形成沟槽。 形成隔离层以填充沟槽。 去除掩模层和隔离层的一部分以露出第一介电层的表面。 去除低电压电路区域的第一电介质层以暴露衬底的表面。 在低电压电路区域的基板上形成厚度小于第一电介质层的第二电介质层。

公开(公告)号：US20060019445A1

公开(公告)日：2006-01-26

申请号：US10907279

申请日：2005-03-28

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L21/336

CPC classification number: H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of manufacturing a non-volatile memory is provided. A substrate is provided and then a plurality of stacked gate structures is formed on the substrate. Each stacked gate structure includes a tunneling dielectric layer, a floating gate, a first inter-gate dielectric layer, a control gate and a cap layer. A source region is formed in the substrate and then a second inter-gate dielectric layer is formed over the substrate. A plurality of polysilicon select gates is formed on one side of the stacked gate structures. The select gates connect the stacked gate structures together to form a memory cell column. A spacer is formed on each sidewall of the memory cell column. A drain region is formed in the substrate on one side of the memory cell column. A silicidation process is carried out to convert the polysilicon constituting the select gate into silicide material.

Abstract translation: 提供一种制造非易失性存储器的方法。 提供衬底，然后在衬底上形成多个堆叠的栅极结构。 每个堆叠的栅极结构包括隧道介电层，浮置栅极，第一栅极间介质层，控制栅极和盖层。 源区域形成在衬底中，然后在衬底上形成第二栅极间电介质层。 多个多晶硅选择栅极形成在堆叠栅极结构的一侧。 选择栅极将堆叠的栅极结构连接在一起以形成存储单元列。 在存储单元列的每个侧壁上形成间隔物。 在存储单元列的一侧上的衬底中形成漏极区。 进行硅化处理以将构成选择栅极的多晶硅转换为硅化物材料。

公开(公告)号：US06277721B1

公开(公告)日：2001-08-21

申请号：US09467005

申请日：1999-12-20

Applicant: Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

Inventor： Tung-Po Chen ,  Hong-Tsz Pan ,  Wen-Yi Hsieh

IPC: H01L213205

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518

Abstract: A method of making a semiconductor device including a MOS transistor provides an insulator formed on a semiconductor substrate and a gate electrode formed on the insulator. Source/drain regions are formed within the substrate on either side of the gate electrode. A layer of titanium is sputtered onto the semiconductor device, and a layer of titanium nitride is direct sputtered over the titanium layer using a titanium nitride target. The device is annealed at a first temperature to form a structure including titanium silicide on the polysilicon electrode, titanium silicide on the surface of the source/drain regions, unreacted titanium over the silicide regions, and titanium nitride over the unreacted metal The unreacted titanium and titanium nitride are removed from the structure, and the structure is annealed at a higher temperature than the first temperature to form a lower resistivity titanium silicide.

Abstract translation: 制造包括MOS晶体管的半导体器件的方法提供形成在半导体衬底上的绝缘体和形成在绝缘体上的栅电极。 源极/漏极区域形成在栅电极两侧的衬底内。 将钛层溅射到半导体器件上，并且使用氮化钛靶将一层氮化钛直接溅射在钛层上。 器件在第一温度下退火以在多晶硅电极上形成包括硅化钛的结构，源极/漏极区域的表面上的硅化钛，硅化物区域上的未反应的钛以及未反应的金属上的氮化钛。未反应的钛和 从结构中除去氮化钛，并且该结构在比第一温度更高的温度下退火以形成较低电阻率的硅化钛。

公开(公告)号：US06255152B1

公开(公告)日：2001-07-03

申请号：US09410690

申请日：1999-10-01

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L218238

CPC classification number: H01L21/823864 ,  H01L21/823814

Abstract: A method of fabricating a CMOS transistor using Si—B layer to form a source/drain extension junction is disclosed. The fabrication includes the steps as follows; First, a p-type semiconductor substrate and an n-well region are provided. Afterwards, a shallow trench isolation (STI) is formed into the p-type semiconductor substrate and the n-well region, thereby forming a plurality of active regions therebetween. A channel is formed into the p-type semiconductor substrate and the n-well region. Then, a PMOSFET gate pattern and an NMOSFET gate pattern are formed over the p-type semiconductor substrate and the n-well region. A first defined photoresist layer is formed over the n-well region. Afterwards, the n−-type dopant is implanted into the p-type semiconductor substrate to form an n−-type lightly doped source/drain. Then the first defined photoresist layer is removed. A first dielectric layer is deposited over the p-type semiconductor substrate and the n-well region. A second defined photoresist layer is formed over the first dielectric layer. Afterwards, a portion of the first dielectric layer is firstly etched over the n-well region. Then an offset spacer is formed on the n-well region during a portion of the first dielectric layer etching step. Next, the second defined photoresist layer is removed. A Si—B (silicon-boron) layer is deposited over the n-well region and the first dielectric layer. The Si—B layer is oxidized to form a BSG layer, thereby firstly diffusing boron atoms into the n-well region to form a p−-type lightly doped source/drain. Afterwards, a second dielectric layer is deposited on the BSG layer. Next, a first BSG spacer and a second BSG spacer are formed, thereby etching a portion of the second dielectric layer, a portion of the BSG layer, and secondly etching a portion of the first dielectric layer. Afterwards, an n+-type heavily doped source/drain is formed into the p-type semiconductor substrate. Next, a p+-type heavily doped source/drain is formed into the n-well region. Finally, the first BSG spacer is annealed, thereby secondly diffusing boron atoms into the bottom region of the first BSG spacer to form a source/drain extension junction in a PMOSFET.

公开(公告)号：US06187674B1

公开(公告)日：2001-02-13

申请号：US09208605

申请日：1998-12-08

Applicant: Tung-Po Chen ,  Yung-Chang Lin ,  Keh-Ching Huang ,  Jacob Chen

Inventor： Tung-Po Chen ,  Yung-Chang Lin ,  Keh-Ching Huang ,  Jacob Chen

IPC: H01L2144

CPC classification number: H01L29/6659 ,  H01L21/28061 ,  H01L21/28247 ,  H01L29/4941

Abstract: A MOS gate manufacturing operation is capable of preventing acid corrosion and station contamination. The manufacturing method includes the steps of sequentially forming a polysilicon layer, a barrier layer, a silicide layer and a cap layer over a silicon substrate, and then etching to form a gate structure. Next, a rapid thermal process is carried out to form an oxide layer over the exposed sidewalls of the barrier layer. Finally, the substrate is cleaned following by the formation of a source/drain region having a lightly doped drain structure on each side of the gate. The thin oxide layer is capable of protecting the barrier layer against acid corrosion without causing any noticeable increase in gate conductivity.

Abstract translation: MOS门制造操作能够防止酸腐蚀和车站污染。 该制造方法包括以下步骤：在硅衬底上顺序地形成多晶硅层，阻挡层，硅化物层和覆盖层，然后蚀刻以形成栅极结构。 接下来，进行快速热处理以在阻挡层的暴露的侧壁上形成氧化物层。 最后，通过在栅极的每一侧上形成具有轻掺杂漏极结构的源极/漏极区域来清洁衬底。 薄氧化物层能够保护阻挡层免受酸腐蚀，而不会导致栅极导电性的任何明显增加。

公开(公告)号：US5858849A

公开(公告)日：1999-01-12

申请号：US47903

申请日：1998-03-25

Applicant: Tung-Po Chen

Inventor： Tung-Po Chen

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L21/265

CPC classification number: H01L21/28052 ,  H01L21/28518 ,  H01L29/665

Abstract: The present invention disclose a salicide process with a self-preamorphization step to reduce the sheet resistance of the source/drain region. The salicide process, comprising the steps of performing a pre-amorphization step on the surface of the silicon and simultaneously forming a metal layer, further contains the substeps of applying a back bias to the bottom of the substrate, using ion metal plasma to transform the surface of the substrate into amorphous silicon, forming a metal layer on the surface of the substrate and then using a thermal process having two stages to transform the metal into the salicide.

Abstract translation: 本发明公开了一种具有自变形步骤以减少源极/漏极区域的薄层电阻的自对准硅化物工艺。 该自对准硅化物工艺包括以下步骤：在硅的表面上进行预非晶化步骤并同时形成金属层，还包括使用离子金属等离子体将背偏压施加到衬底的底部的子步骤，以将 将衬底的表面转变为非晶硅，在衬底的表面上形成金属层，然后使用具有两个阶段的热处理将金属转化成硅化物。

公开(公告)号：US5674777A

公开(公告)日：1997-10-07

申请号：US572495

申请日：1995-12-14

Applicant: Tung-Po Chen ,  Tan-Fu Lei ,  Chun-Yen Chang

Inventor： Tung-Po Chen ,  Tan-Fu Lei ,  Chun-Yen Chang

IPC: H01L21/225 ,  H01L21/20

CPC classification number: H01L21/2254 ,  Y10S148/034 ,  Y10S148/061 ,  Y10S148/144 ,  Y10S148/152

Abstract: The present invention is related to a method for fabricating a silicon electronic device having a boron diffusion source layer, includes steps of: a) providing a silicon substrate; b) depositing a silicon layer on said silicon substrate; and c) growing a silicon-boron binary compound layer on said silicon layer as said boron diffusion source. When the Si-B layer is formed by a UHV/CVD process according to the present invention, the boron concentration in the Si-B binary compound layer will be extraordinary high (up to 1.times.10.sup.21 to 5.times.10.sup.22 atoms/cm.sup.3).

Abstract translation: 本发明涉及一种制造具有硼扩散源层的硅电子器件的方法，包括以下步骤：a）提供硅衬底; b）在所述硅衬底上沉积硅层; 以及c）在所述硅层上生长作为所述硼扩散源的硅 - 硼二元化合物层。 当通过根据本发明的UHV / CVD工艺形成Si-B层时，Si-B二元化合物层中的硼浓度将非常高（高达1×10 21至5×10 22原子/ cm 3）。

公开(公告)号：US07074674B1

公开(公告)日：2006-07-11

申请号：US11160176

申请日：2005-06-13

Applicant: Ko-Hsing Chang ,  Tung-Po Chen ,  Tung-Ming Lai ,  Chen-Chiu Hsue

Inventor： Ko-Hsing Chang ,  Tung-Po Chen ,  Tung-Ming Lai ,  Chen-Chiu Hsue

IPC: H01L21/336

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/7833

Abstract: A method for manufacturing an OTEPROM is described. A tunneling oxide layer, a first conductive layer, a first patterned mask layer are formed on a substrate. A trench is formed in the substrate. An insulating layer is formed to fill the trench. A portion of the first conductive layer destined to form the floating gate is exposed and then a cap layer is formed thereon. The first patterned mask layer is removed and then a second conductive layer and a second patterned mask layer are formed over the substrate. A word line and a floating gate are formed using the second patterned mask layer and the cap layer as a mask. The second patterned mask layer is removed and then source/drain regions are formed in the substrate on both sides of the word line and the floating gate and between the word line and the floating gate.

Abstract translation: 描述了用于制造OTEPROM的方法。 在衬底上形成隧道氧化物层，第一导电层，第一图案化掩模层。 在衬底中形成沟槽。 形成绝缘层以填充沟槽。 目的地形成浮栅的第一导电层的一部分被暴露，然后在其上形成覆盖层。 去除第一图案化掩模层，然后在衬底上形成第二导电层和第二图案化掩模层。 使用第二图案化掩模层和盖层作为掩模形成字线和浮栅。 去除第二图案化掩模层，然后在字线和浮栅两侧以及字线和浮栅之间的衬底中形成源极/漏极区。

公开(公告)号：US06316311B1

公开(公告)日：2001-11-13

申请号：US09203036

申请日：1998-12-01

Applicant: Tung-Po Chen ,  Tong-Yu Chen ,  Keh-Ching Huang ,  Jacob Chen

Inventor： Tung-Po Chen ,  Tong-Yu Chen ,  Keh-Ching Huang ,  Jacob Chen

IPC: H01L218242

CPC classification number: H01L21/76897 ,  H01L27/10873 ,  H01L27/10894

Abstract: A method of forming borderless contacts is provided. A substrate is provided. The substrate has at least a logic region and a memory region. A MOS transistor and a STI structure are formed on the logic region. The MOS transistor comprises a gate, a source/drain region and a cap insulating layer on the gate. An etching stop layer is formed on the substrate to cover the MSO transistor and the STI structure. A dielectric layer is formed in the etching stop layer. The dielectric layer, the etching stop layer and the cap insulating layer are partially removed to form a first opening according to the pattern of a first mask layer. The first opening exposes the gate. According to the pattern of a second mask layer, the dielectric layer and the etching stop layer are partially removed to form openings, which expose the source/drain region, in the dielectric layer.

Abstract translation: 提供了形成无边界接触的方法。 提供基板。 衬底至少具有逻辑区域和存储区域。 在逻辑区域上形成MOS晶体管和STI结构。 MOS晶体管包括栅极，源极/漏极区域和栅极上的帽绝缘层。 在衬底上形成蚀刻停止层以覆盖MSO晶体管和STI结构。 在蚀刻停止层中形成介电层。 根据第一掩模层的图案，介电层，蚀刻停止层和盖绝缘层被部分去除以形成第一开口。 第一个开放暴露了大门。 根据第二掩模层的图案，电介质层和蚀刻停止层被部分地去除以形成在电介质层中暴露源/漏区的开口。

公开(公告)号：US6156633A

公开(公告)日：2000-12-05

申请号：US34261

申请日：1998-03-04

Applicant: Hong-Tsz Pan ,  Tung-Po Chen

Inventor： Hong-Tsz Pan ,  Tung-Po Chen

IPC: H01L21/285 ,  H01L21/44

CPC classification number: H01L21/28518

Abstract: A process for forming high temperature stable self-aligned silicide layer that not only establishes itself smoothly and uniformly despite the use of a high temperature in the siliciding reaction, but also can withstand other subsequent high temperature thermal processing operations and maintaining a stable metal silicide layer profile thereafter. Moreover, desired thickness and uniformity of the metal silicide layer can be obtained by suitably adjusting the amorphous implant parameters, while the use of a titanium nitride cap layer help to stabilize the metal silicide layer during high temperature formation and that a stable and uniform metal silicide layer profile can be ensured even if subsequent high temperature processing operations are performed.

Abstract translation: 用于形成高温稳定的自对准硅化物层的方法，其不仅在硅化反应中使用高温使其自身平滑均匀，而且还可以承受其它随后的高温热处理操作并保持稳定的金属硅化物层 之后的档案。 而且，通过适当地调整非晶态注入参数，可以获得所需的金属硅化物层的厚度和均匀性，而使用氮化钛盖层有助于在高温形成期间稳定金属硅化物层，并且使金属硅化物稳定且均匀 即使执行后续的高温处理操作，也可以确保层的轮廓。