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    Weight plate
    35.
    外观设计
    Weight plate 有权

    公开(公告)号：USD987743S1

    公开(公告)日：2023-05-30

    申请号：US29815263

    申请日：2021-11-12

    Applicant: Zih-Yin Lin

    Designer： Zih-Yin Lin

    Abstract: FIG. 1 is a perspective view of a weight plate showing my new design;
    FIG. 2 is a front elevational view thereof;
    FIG. 3 is a left side elevational view thereof; and,
    FIG. 4 is a top plan view thereof.
    The rear elevational view, the right side elevational view and the bottom plan view of the weight plate are respectively identical to the front elevational view, the side elevational view and the top plan view thereof.

    Schottky rectifier
    38.
    发明授权
    Schottky rectifier 有权
    肖特基整流器

    公开(公告)号：US08816468B2

    公开(公告)日：2014-08-26

    申请号：US13222249

    申请日：2011-08-31

    Applicant: Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

    Inventor： Chih-Wei Hsu ,  Florin Udrea ,  Yih-Yin Lin

    IPC: H01L29/872

    CPC classification number: H01L29/66143 ,  H01L21/22 ,  H01L21/265 ,  H01L29/0619 ,  H01L29/872 ,  H01L29/8725

    Abstract: A semiconductor rectifier includes a semiconductor substrate having a first type of conductivity. A first layer, which is formed on the substrate, has the first type of conductivity and is more lightly doped than the substrate. A second layer having a second type of conductivity is formed on the substrate and a metal layer is disposed over the second layer. The second layer is lightly doped so that a Schottky contact is formed between the metal layer and the second layer. A first electrode is formed over the metal layer and a second electrode is formed on a backside of the substrate.

    Abstract translation: 半导体整流器包括具有第一类导电性的半导体衬底。 形成在基板上的第一层具有第一类导电性，并且比衬底更轻掺杂。 在基板上形成具有第二导电类型的第二层，并且金属层设置在第二层上。 第二层被轻掺杂，使得在金属层和第二层之间形成肖特基接触。 第一电极形成在金属层的上方，第二电极形成在基板的背面。

    Passivation layer for semiconductor devices
    39.
    发明授权
    Passivation layer for semiconductor devices 有权
    半导体器件钝化层

    公开(公告)号：US08643151B2

    公开(公告)日：2014-02-04

    申请号：US13036897

    申请日：2011-02-28

    Applicant: Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    Inventor： Jen-Hao Liu ,  Chyi-Tsong Ni ,  Hsiao-Yin Lin ,  Chung-Min Lin

    IPC: H01L23/58

    CPC classification number: H01L23/3192 ,  H01L21/76834 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An embodiment of the disclosure provides a semiconductor device. The semiconductor device includes a plurality of metallization layers comprising a topmost metallization layer. The topmost metallization layer has two metal features having a thickness T1 and being separated by a gap. A composite passivation layer comprises a HDP CVD oxide layer under a nitride layer. The composite passivation layer is disposed over the metal features and partially fills the gap. The composite passivation layer has a thickness T2 about 20% to 50% of the thickness T1.

    Abstract translation: 本公开的实施例提供一种半导体器件。 半导体器件包括多个金属化层，其包括最上面的金属化层。 最上面的金属化层具有两个具有厚度T1并被间隙隔开的金属特征。 复合钝化层包括氮化物层下的HDP CVD氧化物层。 复合钝化层设置在金属特征上并部分填充间隙。 复合钝化层的厚度T2约为厚度T1的20％至50％。

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