公开(公告)号：US4122541A

公开(公告)日：1978-10-24

申请号：US717668

申请日：1976-08-25

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G06F1/26 ,  G06F12/16 ,  G11C11/417 ,  G11C14/00 ,  G11C16/04 ,  H02J9/06 ,  G11C11/40 ,  G11C8/00

CPC分类号： G11C14/00 ,  G11C11/417 ,  G11C16/0466

摘要： A memory apparatus comprises a plurality of memory cells each having a bistable circuit comprising a pair of field effect transistors, a pair of switching transistors connected between a power supply and each output terminal of said paired field effect transistors, and a plurality of pairs of variable threshold insulated gate field effect transistors connected in parallel with the pair of switching transistors, the variable threshold insulated gate field effect transistors in pair constituting a non-volatile memory cell element, and a plurality of gate control lines connected in common to the gates of the paired variable threshold insulated gate field effect transistors.

摘要翻译： 存储装置包括多个存储单元，每个存储单元具有双稳态电路，该双稳态电路包括一对场效应晶体管，连接在电源和所述成对场效应晶体管的每个输出端之间的一对开关晶体管，以及多对变量 与所述一对开关晶体管并联连接的阈值绝缘栅场效应晶体管，构成非易失性存储单元元件的可变阈值绝缘栅场效应晶体管，以及共同连接到所述栅极的多个栅极控制线 配对可变门限绝缘栅场效应晶体管。

公开(公告)号：US4122531A

公开(公告)日：1978-10-24

申请号：US753020

申请日：1976-12-21

申请人： Keikichi Tamaru ,  Yukimasa Uchida

发明人： Keikichi Tamaru ,  Yukimasa Uchida

IPC分类号： G06F12/04 ,  G06F12/06 ,  G06F12/16 ,  G11C11/417 ,  G11C14/00 ,  G11C16/04 ,  G11C9/06

CPC分类号： G11C16/0466 ,  G11C11/417 ,  G11C14/00

摘要： A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memory plane area; first control lines connected to the second memory plane areas; a first control circuit for selectively driving the control lines to energize the memory cells in the corresponding second memory plane area; a second control line connected to the first memory plane area; and a second control circuit adapted to selectively energize the memory cells of the first memory plane area through the second control line to permit data transfer between the selected memory cell in the first memory plane area and that corresponding memory cell in the second memory area which is energized through the first control line.

摘要翻译： 一种用于具有存储器的存储器的存储器和控制电路，所述存储器包括具有排列成矩阵阵列的多个存储单元的第一存储器平面区域和每个具有排列成矩阵阵列的多个非易失性存储单元的多个第二存储器平面区域， 所述第一存储器平面区域被布置成与所述第二存储器平面区域重叠的关系，并且所述第一存储器平面区域中的存储单元连接到所述第二存储器平面区域中的对应的存储器单元; 连接到第二存储器平面区域的第一控制线; 第一控制电路，用于选择性地驱动控制线以激励对应的第二存储器平面区域中的存储单元; 连接到第一存储器平面区域的第二控制线; 以及第二控制电路，其适于通过所述第二控制线选择性地激励所述第一存储器平面区域的存储器单元，以允许在所述第一存储器平面区域中的所选择的存储器单元与所述第二存储器区域中的对应存储器单元之间的数据传输 通过第一控制线通电。