公开(公告)号：US4122531A

公开(公告)日：1978-10-24

申请号：US753020

申请日：1976-12-21

申请人： Keikichi Tamaru ,  Yukimasa Uchida

发明人： Keikichi Tamaru ,  Yukimasa Uchida

IPC分类号： G06F12/04 ,  G06F12/06 ,  G06F12/16 ,  G11C11/417 ,  G11C14/00 ,  G11C16/04 ,  G11C9/06

CPC分类号： G11C16/0466 ,  G11C11/417 ,  G11C14/00

摘要： A memory and control circuit for the memory with a memory including a first memory plane area having a plurality of memory cells arranged in a matrix array and a plurality of second memory plane areas each having a plurality of nonvolatile memory cells arranged in a matrix array, the first memory plane area being arranged in a superposed relation to the second memory plane area and the memory cell in the first memory plane area being connected to the corresponding memory cell in the second memory plane area; first control lines connected to the second memory plane areas; a first control circuit for selectively driving the control lines to energize the memory cells in the corresponding second memory plane area; a second control line connected to the first memory plane area; and a second control circuit adapted to selectively energize the memory cells of the first memory plane area through the second control line to permit data transfer between the selected memory cell in the first memory plane area and that corresponding memory cell in the second memory area which is energized through the first control line.

摘要翻译： 一种用于具有存储器的存储器的存储器和控制电路，所述存储器包括具有排列成矩阵阵列的多个存储单元的第一存储器平面区域和每个具有排列成矩阵阵列的多个非易失性存储单元的多个第二存储器平面区域， 所述第一存储器平面区域被布置成与所述第二存储器平面区域重叠的关系，并且所述第一存储器平面区域中的存储单元连接到所述第二存储器平面区域中的对应的存储器单元; 连接到第二存储器平面区域的第一控制线; 第一控制电路，用于选择性地驱动控制线以激励对应的第二存储器平面区域中的存储单元; 连接到第一存储器平面区域的第二控制线; 以及第二控制电路，其适于通过所述第二控制线选择性地激励所述第一存储器平面区域的存储器单元，以允许在所述第一存储器平面区域中的所选择的存储器单元与所述第二存储器区域中的对应存储器单元之间的数据传输 通过第一控制线通电。

公开(公告)号：US4641165A

公开(公告)日：1987-02-03

申请号：US475554

申请日：1983-03-15

申请人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

发明人： Tetsuya Iizuka ,  Syuso Fujii ,  Yukimasa Uchida

IPC分类号： G11C11/404 ,  H01L27/108 ,  H01L27/14

CPC分类号： G11C11/404 ,  H01L27/10805

摘要： The dynamic memory device of the present invention is formed on an integrated semiconductor substrate subjected to alpha radiation and comprises a switching transistor having a switching terminal, an input-output terminal and a memory terminal; a bit line couple to said input-output terminal for supplying a charge to said transistor; a word line coupled to said switching terminal for controlling the switching of said transistor; and, an R-C circuit coupled to the memory terminal and comprising a charge storage capacitor for storing the charge supplied from said bit line and for substantially preventing loss of the stored charge due to particle radiation.

摘要翻译： 本发明的动态存储器件形成在经受α辐射的集成半导体衬底上，并且包括具有开关端子，输入输出端子和存储器端子的开关晶体管; 位线耦合到所述输入输出端子，用于向所述晶体管提供电荷; 耦合到所述开关端子用于控制所述晶体管的开关的字线; 以及R-C电路，其耦合到存储器端子并且包括用于存储从所述位线提供的电荷的电荷存储电容器，并且用于基本上防止由于粒子辐射引起的存储电荷的损失。

公开(公告)号：US4489339A

公开(公告)日：1984-12-18

申请号：US551186

申请日：1983-11-14

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L21/331 ,  H01L27/12 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/78 ,  H01L29/78612

摘要： A MOS type semiconductor device effectively supplying potential to a substrate region under the channel forming region of the MOS transistor on an insulating substrate. The potential is supplied to the one conductivity type substrate region under the channel forming region which is provided on an insulating substrate and has an extended portion extending in the channel length direction, through a substrate potential take-out region of one conductivity type connecting to the extended substrate. A gate electrode with an extended gate portion is formed on the substrate region through a gate insulating film, so as to cover the substrate region.

摘要翻译： 一种在绝缘基板上有效地向MOS晶体管的沟道形成区域下方的衬底区域提供电位的MOS型半导体器件。 电位被提供给设置在绝缘基板上的沟道形成区域下方的一个导电型基板区域，并且具有沿着沟道长度方向延伸的延伸部分，通过一个导电类型的基板电位取出区域连接到 延长基板。 具有延伸栅极部分的栅电极通过栅极绝缘膜形成在衬底区域上，以覆盖衬底区域。

公开(公告)号：US4467452A

公开(公告)日：1984-08-21

申请号：US331066

申请日：1981-12-15

申请人： Shozo Saito ,  Yukimasa Uchida ,  Kazuhiko Hashimoto ,  Norio Endo

发明人： Shozo Saito ,  Yukimasa Uchida ,  Kazuhiko Hashimoto ,  Norio Endo

IPC分类号： H01L29/792 ,  G11C11/40 ,  H01L29/78

CPC分类号： H01L29/792

摘要： A nonvolatile semiconductor memory device having a gate insulating film with a memory function. An impurity layer having the same conductivity type as that of the substrate region is formed in that substrate region, underlying the gate insulating film having a memory function, in which a channel is formed. The impurity layer has an impurity profile in which a peak of an impurity concentration is in the region distanced by 500 .ANG. or less from the surface of the substrate region and the impurity concentration is 1.times.10.sup.18 cm.sup.-3 or less in the region at the depth of 500 .ANG. or more.

摘要翻译： 一种具有具有记忆功能的栅极绝缘膜的非易失性半导体存储器件。 在其中形成沟道的具有记忆功能的栅极绝缘膜下方的衬底区域中形成具有与衬底区域相同的导电类型的杂质层。 杂质层具有杂质浓度在距离衬底区域的表面远离500或更小的区域中的杂质分布，并且在深度的区域中杂质浓度为1×10 18 cm -3或更小 500 ANGSTROM以上。

公开(公告)号：US4385308A

公开(公告)日：1983-05-24

申请号：US151599

申请日：1980-05-20

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02 ,  H01L29/04 ,  H01L29/34

CPC分类号： H01L29/7881 ,  H01L29/78

摘要： A silicon nitride layer and a memory gate electrode are successively formed over a portion of a principal surface of a semiconductor substrate between drain and source regions formed therein and adjacent to the drain region via a thin silicon dioxide layer. A portion of the substrate principal surface, to which the source region is contiguous, is covered by a thick silicon dioxide layer, and a selection gate electrode is buried in the thick silicon dioxide layer. This two-input gate transistor construction constitutes a memory cell.

摘要翻译： 在形成于其中的漏极和源极区域之间的半导体衬底的主表面的一部分上，通过薄的二氧化硅层与漏极区域相邻地形成氮化硅层和存储栅电极。 源极区域邻接的衬底主表面的一部分被厚的二氧化硅层覆盖，并且选择栅电极被埋在厚的二氧化硅层中。 该双输入栅极晶体管构造构成存储单元。

公开(公告)号：US5185567A

公开(公告)日：1993-02-09

申请号：US726810

申请日：1991-07-08

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H03K19/00 ,  G05F1/577 ,  H02J1/10

CPC分类号： H02J1/10 ,  G05F1/577 ,  Y10T307/313

摘要： Each end of a power wiring is connected to a first or a second power supply circuit, respectively. These two power supply circuits are activated alternately allowing for some time-overlap. As a result, current flowing in the wiring changes its flowing direction alternately to prevent the degradation of the wiring due to the electro-migration phenomena.

摘要翻译： 电源线的每一端分别连接到第一或第二电源电路。 这两个电源电路交替激活允许一些时间重叠。 结果，在布线中流动的电流交替地改变其流动方向，以防止由于电迁移现象引起的布线的劣化。

公开(公告)号：US4792834A

公开(公告)日：1988-12-20

申请号：US150505

申请日：1988-02-01

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L27/10 ,  G11C11/40 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8244 ,  H01L27/04 ,  H01L27/108 ,  H01L27/11 ,  H01L29/78

CPC分类号： H01L27/10829

摘要： Disclosed is a semiconductor memory device which has a transfer transistor of a MOS structure on a surface of a semiconductor body, and a trenched capacitor having a groove which is formed so as to extend from a surface of the semiconductor body to a certain depth thereof and an electrode which is formed from a bottom portion of the groove to at least a level above an opening of the groove, the source region of the transfer transistor being connected to the electrode of the trenched capacitor and the drain region thereof being connected to a bit line.

摘要翻译： 公开了一种半导体存储器件，其具有在半导体本体的表面上的MOS结构的转移晶体管，以及沟槽电容器，其具有形成为从半导体本体的表面延伸到其一定深度的沟槽， 由槽的底部形成至少在槽的开口上方的电极，转移晶体管的源极区域与沟槽电容器的电极连接，漏极区域连接到位 线。

公开(公告)号：US4532607A

公开(公告)日：1985-07-30

申请号：US398925

申请日：1982-07-16

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C17/18 ,  G11C29/00 ,  G11C11/34 ,  G11C17/00

CPC分类号： G11C29/781 ,  G11C17/18 ,  G11C29/789

摘要： A programmable circuit has a fuse element grounded at one end and melted or not melted according to the data to be programmed and a select circuit for selectively producing either of two signals according to "melted" or "not melted" states of the fuse element. The other end of the fuse element is connected through a switching element to the power source terminal, and through a latch circuit to the select circuit. By turning on the switching element at least one time, a level corresponding to a melted state of the fuse element is latched in the latch circuit.

摘要翻译： 可编程电路具有根据要编程的数据在一端接地并熔化或不熔化的熔丝元件，以及选择电路，用于根据熔丝元件的“熔化”或“未熔化”状态选择性地产生两个信号。 熔丝元件的另一端通过开关元件连接到电源端子，并通过锁存电路连接到选择电路。 通过至少一次接通开关元件，与熔丝元件的熔化状态对应的电平被锁存在锁存电路中。

公开(公告)号：US4168537A

公开(公告)日：1979-09-18

申请号：US778023

申请日：1977-03-15

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： G11C11/417 ,  G11C14/00 ,  G11C16/04 ,  H03K3/356 ,  G11C7/00 ,  G11C11/34

CPC分类号： H03K3/356008 ,  G11C11/417 ,  G11C14/00 ,  G11C16/0466

摘要： A nonvolatile memory system includes a memory array. The unit memory cell includes a bistable circuit having a pair of bistable output points and at least one pair of variable threshold field effect elements connected to the bistable points. The memory system further includes, decoders for selecting at least one unit cell, a pair of data lines to be connected to the digit lines of the selected unit cell or cells, a first means for driving the decoders to select at least one unit cell, a second means, external to the memory cells, for causing the bistable points in the selected memory cell or cells to be set to a ground reference level through the digit lines, and a third means for causing a read control signal from a corresponding control signal generator to be supplied to the variable threshold field effect elements so as to transfer data stored in the threshold field effect elements to the bistable points. The second means allows the bistable points to be set to the reference potential and any non-volatile memory cell can be read at any desired time during the "ON" state of the power supply source. Since the second means is external to the memory cells, a conventional memory cell array can be used without modification, and no great chip area is required in arranging such cells. During a read or write transfer between the bistable points and non-volatile memory cell sections it is possible to select individual unit cells or all cells at once.

摘要翻译： 非易失性存储器系统包括存储器阵列。 单元存储单元包括具有一对双稳态输出点和连接到双稳态点的至少一对可变阈值场效应元件的双稳态电路。 存储系统还包括用于选择至少一个单位单元的解码器，要连接到所选择的单位单元或单元的数字线的一对数据线，用于驱动解码器以选择至少一个单位单元的第一装置， 存储单元外部的第二装置，用于使所选择的存储单元或单元中的双稳​​态点通过数字线被设置为接地参考电平;以及第三装置，用于使来自相应控制信号的读控制信号 发生器被提供给可变阈值场效应元件，以将存储在阈值场效应元素中的数据传送到双稳态点。 第二装置允许将双稳态点设置为参考电位，并且可以在电源的“接通”状态期间的任何期望的时间读取任何非易失性存储单元。 由于第二装置在存储器单元的外部，因此可以使用传统的存储单元阵列而无需修改，并且在布置这些单元时不需要很大的芯片面积。 在双稳态点和非易失性存储单元部分之间的读或写传输期间，可以一次选择单个单元单元或所有单元。

公开(公告)号：US5428236A

公开(公告)日：1995-06-27

申请号：US857727

申请日：1992-03-26

申请人： Yukimasa Uchida

发明人： Yukimasa Uchida

IPC分类号： H01L27/108

CPC分类号： H01L27/10829

摘要： Disclosed is a memory having a p-type semiconductor substrate having a high impurity concentration a p-type semiconductor layer is formed on thereof; a groove which is formed so as to extend from a surface of the semiconductor layer to a position inside the semiconductor substrate; an impurity diffused region which is formed on portions of the semiconductor layer and the semiconductor substrate which define the groove; and an electrode which is formed from the groove to level at least above an opening of the groove through capacitor insulation film, the impurity diffused region, capacitor insulation film and electrode constituting trenched capacitor in which the electrode serves first capacitor electrode and the impurity diffused region serves as a second capacitor electrode.

摘要翻译： 公开了具有杂质浓度高的p型半导体衬底的存储器，其上形成有p型半导体层; 形成为从半导体层的表面延伸到半导体衬底内的位置的槽; 形成在限定所述沟槽的所述半导体层和所述半导体衬底的部分上的杂质扩散区域; 以及由沟槽形成的电极，通过电容绝缘膜，杂质扩散区域，电容器绝缘膜和构成沟槽电容器的电极的至少在沟槽的上方平坦化，其中电极用作第一电容器电极和杂质扩散区域 用作第二电容器电极。