公开(公告)号：US20240129236A1

公开(公告)日：2024-04-18

申请号：US18454782

申请日：2023-08-23

Applicant: ZHEJIANG LAB

Inventor： Yuan LIANG ,  Geyang XIAO ,  Yuanhao HE ,  Tao ZOU ,  Ruyun ZHANG ,  Xiaofeng CHENG

IPC: H04L47/12 ,  G06N20/00 ,  H04L41/16

CPC classification number: H04L47/12 ,  G06N20/00 ,  H04L41/16

Abstract: The present application discloses a DQN-based distributed computing network coordinate flow scheduling system and method. The method includes: establishing environmental feature data based on distributed computing task information and a congestion situation of a port queue in a programmable forwarding platform on a data plane, establishing and training a deep reinforcement learning intelligent agent based on an action value network and a target network in DQN, and the deep reinforcement learning intelligent agent outputting abstract actions; receiving, by a policy mapper, the abstract actions and mapping them into an executable coordinate flow scheduling policy; executing, by the programmable forwarding platform, the executable coordinate flow scheduling policy and updating the congestion situation of the port queue; and recording, a policy gainer, a completion time of a distributed computing task as a real-time reward of the deep reinforcement learning intelligent agent and iteratively optimizing the deep reinforcement learning intelligent agent.

公开(公告)号：US20240118897A1

公开(公告)日：2024-04-11

申请号：US18071978

申请日：2022-11-30

Applicant: ZHEJIANG LAB

Inventor： Hongsheng WANG ,  Guang CHEN ,  Lingfang ZENG ,  Aimin PAN

IPC: G06F9/38

CPC classification number: G06F9/3838 ,  G06F9/3885

Abstract: Disclosed are an instruction execution method and apparatus for graph computation. The method includes the following steps: S1: sending operators of each node in a computational graph used for neural network computation to an operator interpreter; S2: building, by the operator interpreter, instructions in operation; S3: defining an instruction dependency relationship; S4: building an instruction dependency relationship graph; S5: building a topological order of parallel instructions; S6: scheduling the parallel instructions to hardware resources; S7: building shortest schedules for the parallel instructions: the shortest time required to execute the parallel instructions under the condition of limited hardware resources; and S8: releasing the completed instructions.

公开(公告)号：US20240104341A1

公开(公告)日：2024-03-28

申请号：US17992822

申请日：2022-11-22

Applicant: ZHEJIANG LAB

Inventor： Hongsheng WANG ,  Guang CHEN ,  Lingfang ZENG

IPC: G06N3/04

CPC classification number: G06N3/04

Abstract: A memory optimization method includes: compiling a neural network into a computational graph for neural network computation on a computer; transforming the computational graph into a topological graph; constructing a life cycle relationship graph of tensor variables in the computational graph; and analyzing a life cycle relationship among tensor variables in a node of the computational graph; iteratively merging those tensor variables connected by lines of the second type and caching into a memory any tensor variable that goes beyond a number of idle registers and is not allocated to a register, until all tensor variables that go beyond the number of the idle registers and are not allocated to registers are cached into the memory; caching any node of the life cycle relationship graph with a degree smaller than a number of registers into a stack.

公开(公告)号：US11941532B2

公开(公告)日：2024-03-26

申请号：US17726563

申请日：2022-04-22

Applicant: ZHEJIANG LAB

Inventor： Hongsheng Wang ,  Wei Hua ,  Hujun Bao ,  Fei Yang

IPC: G06N3/10 ,  G06N3/04

CPC classification number: G06N3/10 ,  G06N3/04

Abstract: Disclosed is a method for adapting a deep learning framework to a hardware device based on a unified backend engine, which comprises the following steps: S1, adding the unified backend engine to the deep learning framework; S2, adding the unified backend engine to the hardware device; S3, converting a computational graph, wherein the computational graph compiled and generated by the deep learning framework is converted into an intermediate representation of the unified backend engine; S4, compiling the intermediate representation, wherein the unified backend engine compiles the intermediate representation on the hardware device to generate an executable object; S5, running the executable object, wherein the deep learning framework runs the executable object on the hardware device; S6: managing memory of the unified backend engine.

公开(公告)号：US11934887B1

公开(公告)日：2024-03-19

申请号：US18466384

申请日：2023-09-13

Applicant: ZHEJIANG LAB

Inventor： Hongsheng Wang ,  Fei Wu ,  Guang Chen ,  Feng Lin

IPC: G06F9/50 ,  G06F8/41

CPC classification number: G06F9/5072 ,  G06F8/41 ,  G06F9/5066 ,  G06F2209/5016 ,  G06F2209/5017

Abstract: The present disclosure discloses a distributed model compilation system. A master node of the system determines the logic calculation graph of the model based on model information, divides the logic calculation graph into multiple logic calculation sub-graphs, generates a distributing message for each logic calculation sub-graph, and then transmits the distributing message to a slave node. Each of the slave nodes allocates a local computing resource to compile the logic calculation sub-graph based on the received distributing message, and transmits compilation completion information to the master node. The master node determines the completion of model compilation based on the compilation completion information returned by each slave node, and executes the target work based on the compiled model.

公开(公告)号：US20240078678A1

公开(公告)日：2024-03-07

申请号：US18360796

申请日：2023-07-27

Applicant: ZHEJIANG LAB

Inventor： Jingsong LI ,  Jun LI ,  Baochen WANG ,  Zhuoxin LI ,  Yu TIAN ,  Tianshu ZHOU

IPC: G06T7/00

CPC classification number: G06T7/0014 ,  G06T2207/10088 ,  G06T2207/30016

Abstract: The present application discloses a system and a device for functional connectivity matrix processing based on feature selection using a filtering method, which comprises the following steps: acquiring a preprocessed resting state brain functional magnetic resonance image of a subject; extracting time series; calculating a Pearson correlation coefficient to obtain a Pearson correlation coefficient matrix; vectorizing the Pearson correlation coefficient matrix; calculating quantitative correlation indices using a filtering method, and selecting a quantitative correlation index based on a preset threshold; performing weighting processing a selected functional connectivity feature by using the corresponding quantitative correlation index with high correlation with a disease diagnosis result to obtain a functional connectivity matrix; and obtaining a prediction result from the functional connectivity matrix.

公开(公告)号：US20240071607A1

公开(公告)日：2024-02-29

申请号：US18363701

申请日：2023-08-01

Applicant: ZHEJIANG LAB

Inventor： Jingsong LI ,  Wenchao XIANG ,  Guangyuan DENG ,  Tianshu ZHOU ,  Yu TIAN

IPC: G16H40/20 ,  G06F9/48 ,  G06F16/25 ,  G16H10/60

CPC classification number: G16H40/20 ,  G06F9/4881 ,  G06F16/254 ,  G16H10/60

Abstract: The present disclosure discloses a medical ETL task dispatching method, system and apparatus based on multiple centers. The method includes following steps: step S1: testing and verifying ETL tasks; step S2: deploying the ETL tasks to a hospital center, and dispatching the ETL tasks to a plurality of executors for execution; step S3: screening an executor set meeting resource demands of ETL tasks to be dispatched; step S4: calculating a current task load of each executor in the executor set; step S5: selecting the executor with a minimum current task load to execute the ETL tasks; and step S6: selecting, by the dispatching machine, the ETL tasks from executor active queues according to a priority for execution. The present disclosure selects the most suitable executor by analyzing a serving index as a task to be dispatched on a current dispatching machine.

公开(公告)号：US20240054339A1

公开(公告)日：2024-02-15

申请号：US17990617

申请日：2022-11-18

Applicant: ZHEJIANG LAB

Inventor： Hongyang CHEN ,  Bingyang HU ,  Qingguo QI ,  Zhao LI

IPC: G06N3/08

CPC classification number: G06N3/08

Abstract: Disclosed are a method and system for predicting spatio-temporal perception information based on a graph neural network. The method includes the following steps: step S1: constructing a perception data monitoring network, and acquiring original perception data through data acquisition nodes in the perception data monitoring network; step S2: pre-processing the original perception data and converting the same into spatio-temporal graph perception data; step S3: constructing a graph neural network model, and training parameters of the graph neural network model by using the spatio-temporal graph perception data; and step S4: inputting given spatio-temporal graph perception data to the trained graph neural network model and outputting a predicted value, and sending early warning information when the predicted value exceeds a preset threshold.

公开(公告)号：US11900618B2

公开(公告)日：2024-02-13

申请号：US18338328

申请日：2023-06-20

Applicant: ZHEJIANG LAB

Inventor： Yechi Ma ,  Wei Hua ,  Quan Feng ,  Shun Zhang

IPC: G06T7/246

CPC classification number: G06T7/251 ,  G06T2207/10028 ,  G06T2207/20081 ,  G06T2207/20084

Abstract: A system and a method for detecting a moving target based on multi-frame point clouds. The system comprises a voxel feature extraction module; a transformer module used for matching and fusing the feature tensor sequence, fusing a first feature tensor with a second feature tensor, fusing the fused result with a third feature tensor, fusing the fused result with a fourth feature tensor, and repeating the fusing steps with a next feature tensor to obtain a final fused feature tensor; and an identification module used for extracting features from the final fused feature tensor and outputting detection information of a target. The method comprises the following steps: S1, constructing each system module; S2, training the model by the data in a training set; S3, predicting by the trained model.

公开(公告)号：US11887964B1

公开(公告)日：2024-01-30

申请号：US18298379

申请日：2023-04-11

Applicant: ZHEJIANG LAB

Inventor： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/306

CPC classification number: H01L25/0655 ,  H01L21/30625 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/182

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.