公开(公告)号：US12112115B2

公开(公告)日：2024-10-08

申请号：US18328800

申请日：2023-06-05

Applicant: ZHEJIANG LAB

Inventor： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: G06F30/396 ,  G06F115/02 ,  G06F119/22 ,  H01L27/02

CPC classification number: G06F30/396 ,  H01L27/0207 ,  G06F2115/02 ,  G06F2119/22

Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.

公开(公告)号：US11983481B2

公开(公告)日：2024-05-14

申请号：US18351464

申请日：2023-07-12

Applicant: ZHEJIANG LAB

Inventor： Zhiquan Wan ,  Shunbin Li ,  Ruyun Zhang ,  Weihao Wang ,  Qingwen Deng

IPC: G06F30/398 ,  G06F30/392 ,  G06F117/12

CPC classification number: G06F30/398 ,  G06F30/392 ,  G06F2117/12

Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.

公开(公告)号：US11776879B1

公开(公告)日：2023-10-03

申请号：US18306948

申请日：2023-04-25

Applicant: ZHEJIANG LAB

Inventor： Guandong Liu ,  Weihao Wang ,  Shunbin Li ,  Ruyun Zhang

IPC: H01L23/02 ,  H01L23/473 ,  H01L23/498 ,  H01L23/31 ,  H01L23/367 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L23/3128 ,  H01L23/367 ,  H01L23/49816 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/32245 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/182

Abstract: The present disclosure discloses a three-dimensional stacked package structure with a micro-channel heat dissipation structure and a packaging method thereof. The three-dimensional stacked package structure includes a chip package portion comprising a multi-layered structure with stacked chips, wherein the stacked chips are provided with through silicon vias and packaged in a three-dimensional stacked packaging manner and a silicon substrate package portion comprising a silicon substrate. The silicon substrate is provided with micro bumps which are to be interconnected with external lead wires. The chip package portion is assembled on the silicon substrate by bonding with the micro bumps. The stacked chips are etched with micro-channels and through holes corresponding to each other. The micro-channels are for coolant flowing in a horizontal direction, and the through holes are for coolant flowing in upper and lower layers. Sealing rings are arranged around the micro-channels and the through holes.

公开(公告)号：US11887964B1

公开(公告)日：2024-01-30

申请号：US18298379

申请日：2023-04-11

Applicant: ZHEJIANG LAB

Inventor： Shunbin Li ,  Weihao Wang ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L21/306

CPC classification number: H01L25/0655 ,  H01L21/30625 ,  H01L21/486 ,  H01L21/565 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5383 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2924/182

Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.

公开(公告)号：US11876071B1

公开(公告)日：2024-01-16

申请号：US18328797

申请日：2023-06-05

Applicant: ZHEJIANG LAB

Inventor： Weihao Wang ,  Shunbin Li ,  Guandong Liu ,  Ruyun Zhang ,  Qinrang Liu ,  Zhiquan Wan ,  Jianliang Shen

IPC: H01L23/00 ,  H01L23/538

CPC classification number: H01L24/81 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5382 ,  H01L23/5389 ,  H01L24/11 ,  H01L24/14 ,  H01L2224/11462 ,  H01L2224/1403 ,  H01L2224/145 ,  H01L2224/14131

Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.