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公开(公告)号：US12112991B1
公开(公告)日：2024-10-08
申请号：US18497947
申请日：2023-10-30
Applicant: ZHEJIANG LAB
Inventor： Qingwen Deng , Kun Zhang , Ruyun Zhang
Abstract: A system on wafer assembly structure and an assembly method thereof. The system on wafer assembly structure comprises: a wafer layer, a dielectric layer and a circuit board layer sequentially stacked, and each provided with a bonding region, a testing region and an alignment region, respectively, a first assembly, and a second assembly, wherein the first assembly is arranged on one side of the wafer layer far away from the dielectric layer, and comprises a bearing portion and at least one latch portion connected with each other, and the bearing portion is detachably connected with the wafer layer. The second assembly is at least partially arranged around the first assembly. The second assembly has a hole portion for accommodating a latch portion, and the inner diameter of the hole portion is larger than the outer diameter of the latch portion.
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公开(公告)号：US12032933B2
公开(公告)日：2024-07-09
申请号：US18495707
申请日：2023-10-26
Applicant: ZHEJIANG LAB
Inventor： Lei Xue , Tao Zou , Ruyun Zhang , Jun Zhu
CPC classification number: G06F8/443 , G06F9/44505
Abstract: The present disclosure discloses a compiling system for a compiling system and a compiling method for a programmable network element. Aiming at the diversified requirements of network modals for the underlying hardware resources, the system realizes the integration and fusion mechanism of computing/storage/forwarding/security, and abstracts network element equipment including heterogeneous hardware resources and isomeric hardware resources into a logical network element irrelevant to the underlying hardware; performs advanced abstract encapsulation on the heterogeneous hardware resources and isomeric hardware resources, supports flexible calling of underlying hardware and software resources, uses the technology of functional equivalent replacement between heterogeneous hardware resources and isomeric hardware resources, realizes switching and co-processing of network modals among hardware resources according to actual requirements, allocates heterogeneous hardware resources according to modal characteristics, and calls various compilers to automatically generate and optimize modal packet processing pipelines.
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公开(公告)号：US12021751B2
公开(公告)日：2024-06-25
申请号：US18454782
申请日：2023-08-23
Applicant: ZHEJIANG LAB
Inventor： Yuan Liang , Geyang Xiao , Yuanhao He , Tao Zou , Ruyun Zhang , Xiaofeng Cheng
Abstract: The present application discloses a DQN-based distributed computing network coordinate flow scheduling system and method. The method includes: establishing environmental feature data based on distributed computing task information and a congestion situation of a port queue in a programmable forwarding platform on a data plane, establishing and training a deep reinforcement learning intelligent agent based on an action value network and a target network in DQN, and the deep reinforcement learning intelligent agent outputting abstract actions; receiving, by a policy mapper, the abstract actions and mapping them into an executable coordinate flow scheduling policy; executing, by the programmable forwarding platform, the executable coordinate flow scheduling policy and updating the congestion situation of the port queue; and recording, a policy gainer, a completion time of a distributed computing task as a real-time reward of the deep reinforcement learning intelligent agent and iteratively optimizing the deep reinforcement learning intelligent agent.
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公开(公告)号：US11887964B1
公开(公告)日：2024-01-30
申请号：US18298379
申请日：2023-04-11
Applicant: ZHEJIANG LAB
Inventor： Shunbin Li , Weihao Wang , Ruyun Zhang , Qinrang Liu , Zhiquan Wan , Jianliang Shen
IPC: H01L21/00 , H01L25/065 , H01L23/498 , H01L23/538 , H01L23/00 , H01L21/48 , H01L21/56 , H01L21/306
CPC classification number: H01L25/0655 , H01L21/30625 , H01L21/486 , H01L21/565 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/5383 , H01L24/16 , H01L24/81 , H01L2224/16235 , H01L2224/81192 , H01L2924/182
Abstract: A wafer-level heterogeneous dies integration structure and method are provided. The integration structure includes a wafer substrate, a silicon interposer, heterogeneous dies, and a configuration substrate. A standard integration module is defined by the heterogeneous dies connected to the silicon interposer. The standard integration module is connected to an upper surface of the wafer substrate, and the configuration substrate is connected to a lower surface of the wafer substrate. The wafer substrate is connected to the configuration substrate via Through Silicon Vias on lower surface of the wafer substrate. And the upper surface of the wafer substrate is provided with Re-distributed Layers and a standardized micro bump array to form standard integration zone connected to the standard integration module.
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公开(公告)号：US11876071B1
公开(公告)日：2024-01-16
申请号：US18328797
申请日：2023-06-05
Applicant: ZHEJIANG LAB
Inventor： Weihao Wang , Shunbin Li , Guandong Liu , Ruyun Zhang , Qinrang Liu , Zhiquan Wan , Jianliang Shen
IPC: H01L23/00 , H01L23/538
CPC classification number: H01L24/81 , H01L23/538 , H01L23/5381 , H01L23/5382 , H01L23/5389 , H01L24/11 , H01L24/14 , H01L2224/11462 , H01L2224/1403 , H01L2224/145 , H01L2224/14131
Abstract: A system-on-wafer structure and a fabrication method. The structure includes a wafer substrate, an integrated chiplet, a system configuration board and a thermal module. The wafer substrate and the integrated chiplet are bonded through a wafer micro bump array and a chiplet micro bump array. The wafer substrate and the system configuration board are bonded through a copper pillar array on wafer substrate topside and a pad on system configuration board backside. A molding layer is provided between the wafer substrate and the system configuration board, and is configured to mold the wafer substrate, the integrated chiplet and the copper pillar array. Integrated chiplet are electrically connected to each other through a re-distributed layer in wafer substrate. The integrated chiplet is electrically connected to the system configuration board through the re-distributed layer and the copper pillar array. The thermal module is attached to the backside of the wafer substrate.
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Patent Agency Ranking
公开(公告)号：US11860893B1
公开(公告)日：2024-01-02
申请号：US17981368
申请日：2022-11-04
Applicant: ZHEJIANG LAB
Inventor： Peilei Wang , Ruyun Zhang , Tao Zou , Shunbin Li , Peilong Huang
CPC classification number: G06F16/27 , G06F9/54 , G06F16/256 , H04L67/56
Abstract: Disclosed are an input/output proxy method and apparatus for a mimic Redis database. Through a pseudo server module, it is ensured that the interface of the Redis database is consistent with the external interface of the native Redis, so that it is convenient to implant the Redis database into arbitrary Redis application scenarios; the isolation of the modules inside is realized by independent processes, thus facilitating independent development, maintenance and expansion; and the synchronization function is integrated into the input/output proxy to achieve resource reuse; for the synchronization function, the random credit attenuation mechanism is cleverly utilized to ensure the synchronization function while taking into account the saving of resources.
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公开(公告)号：US11431632B1
公开(公告)日：2022-08-30
申请号：US17739173
申请日：2022-05-09
Applicant: Zhejiang Lab
Inventor： Qi Xu , Hanguang Luo , Tao Zou , Ruyun Zhang , Geyang Xiao , Wanxin Gao , Huifeng Zhang , Congqi Shen
IPC: H04L45/745 , H04L45/50 , H04L45/00
Abstract: The present invention relates to the technical field of computer networking, in particular to an ID/location hybrid forwarding method based on source routing, including a message format based on an extension header of a MobilityFirst protocol, a source routing forwarding mechanism based on ID identifiers and a source routing forwarding mechanism based on location identifiers. Through the method of the present invention, the source routing forwarding mechanism based on ID identifiers can be adopted in the access domains of the MobilityFirst network to realize the internetworking of intra-domain networks, and the source routing forwarding mechanism based on location identifiers in the core domain realizes the interconnection of inter-domain networks; the method greatly simplifies the processing flow of the data plane of the MobilityFirst network, and meanwhile reserves the design that the ID identifiers and the location identifiers are separated, thereby effectively supporting intra-domain and inter-domain mobile data forwarding.
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公开(公告)号：US12112115B2
公开(公告)日：2024-10-08
申请号：US18328800
申请日：2023-06-05
Applicant: ZHEJIANG LAB
Inventor： Shunbin Li , Weihao Wang , Ruyun Zhang , Qinrang Liu , Zhiquan Wan , Jianliang Shen
IPC: G06F30/396 , G06F115/02 , G06F119/22 , H01L27/02
CPC classification number: G06F30/396 , H01L27/0207 , G06F2115/02 , G06F2119/22
Abstract: A routing structure and a method of a wafer substrate with standard integration zone for integration on-wafer, which comprises a core voltage network, an interconnection signal network, a clock signal network and a ground network, wherein the core voltage network and the interconnection signal network belong to a top metal layer, the clock signal network is located in a inner metal layer, and the ground network is located in a bottom metal layer. The pins provided on the standard zone include core voltage pins, interconnection signal pins, clock signal pins, ground pins, and complex function pins. The complex function pins are directly connected to the outside of the system by TSV at the bottom of the wafer, and the other pins are connected by their signal networks. The present disclosure solves the yield problem with few metal layers of the wafer substrate for SoW.
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公开(公告)号：US12015548B2
公开(公告)日：2024-06-18
申请号：US18542823
申请日：2023-12-18
Applicant: ZHEJIANG LAB
Inventor： Congqi Shen , Huifeng Zhang , Tao Zou , Ruyun Zhang
Abstract: A method and a device for identification management and optimized forwarding in a large-scale polymorphic network, the method comprising the follow steps: S1, constructing a polymorphic backbone network; S2, modality identification management; S3, determining a modality to be forwarded; S4, configuring a flow table for a switching node; S5, receiving a packet by a balanced distributor, and preliminarily parsing the type of the packet; S6, parsing key field information in the packet, determining the switching nodes to be allocated according to the key field information, and transmitting the key field information to the corresponding switching node; S7, the switching node matching the stored flow table according to the key field information to determine a correct forwarding action.
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公开(公告)号：US11983481B2
公开(公告)日：2024-05-14
申请号：US18351464
申请日：2023-07-12
Applicant: ZHEJIANG LAB
Inventor： Zhiquan Wan , Shunbin Li , Ruyun Zhang , Weihao Wang , Qingwen Deng
IPC: G06F30/398 , G06F30/392 , G06F117/12
CPC classification number: G06F30/398 , G06F30/392 , G06F2117/12
Abstract: The present disclosure relates to software-defined methods and apparatuses for designing a wafer-level switching system, including: determining wafer-level switching system layout constraints; constructing a target wafer-level switching system and determining parameters, and designing a logical topology of a switching network; designing a layout of the switching chiplets on the wafer substrate; respectively designing interface structures of external chiplets and internal chiplets; configuring a switching mode and an enable state of each port of the switching chiplets; ending the process when the target logical topology can be achieved by the wafer-level switching system; otherwise, reconstructing a logical topology of a switching network and mapping it to the substrate.
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