公开(公告)号：US11379941B2

公开(公告)日：2022-07-05

申请号：US15415823

申请日：2017-01-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Todd Martin ,  Mangesh P. Nijasure ,  Randy W. Ramsey ,  Michael Mantor ,  Laurent Lefebvre

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/40

Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

公开(公告)号：US10740074B2

公开(公告)日：2020-08-11

申请号：US16227741

申请日：2018-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian J. Favela ,  Todd Martin ,  Robert A. Gottlieb

IPC: G06F8/41 ,  G06T1/20

Abstract: A method and system for compiler optimization includes analyzing a representation of source code to identify an original conditional construct having both a high-latency instruction and one or more instructions dependent on the high-latency instruction in a branch of the conditional construct. A set of one or more instructions following the conditional construct in the representation of source code and independent of the high-latency instruction is selected. An optimized representation of the source code is generated, whereby the optimized representation replaces the original conditional construct with a first split conditional construct positioned prior to the selected set of one or more instructions and a second split conditional construct positioned following the selected set of one or more instructions, The method further includes generating an executable representation of the source code based on the optimized representation of the source code.

公开(公告)号：US10388056B2

公开(公告)日：2019-08-20

申请号：US15417063

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Mangesh P. Nijasure ,  Todd Martin ,  Michael Mantor

IPC: G06T15/00 ,  G06T11/40 ,  G06F9/44

Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.

公开(公告)号：US10210650B1

公开(公告)日：2019-02-19

申请号：US15828055

申请日：2017-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/48 ,  G06F9/50

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

公开(公告)号：US20180181306A1

公开(公告)日：2018-06-28

申请号：US15389204

申请日：2016-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Guohua Jin ,  Todd Martin

IPC: G06F3/06

CPC classification number: G06T1/60 ,  G06F9/46 ,  G06T15/005 ,  G06T17/20

Abstract: A method and apparatus of copying data from a first memory location to a second memory location includes performing a copy operation selected out of one or more copy operations. The copy operations include performing interleaved data copying, performing a full wavefront copy operation, copying all data to a local data store (LDS) prior to copying to the second memory location, or pipelining the data for copying. The copy operation is applied to copy the data from the first location to the second memory location.