公开(公告)号：US20230206379A1

公开(公告)日：2023-06-29

申请号：US17564049

申请日：2021-12-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Fuad Ashkar ,  Mangesh P. Nijasure ,  Rakan Z. Khraisha ,  Manu Rastogi

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06T15/005 ,  G06T15/80

Abstract: Methods and systems are disclosed for inline suspension of an accelerated processing unit (APU). Techniques include receiving a packet, including a mode of operation and commands to be executed by the APU; suspending execution of commands received in previous packets when the mode of operation is a suspension initiation mode; and executing, by the APU, the commands in the received packet. The execution of the suspended commands is restored when the mode of operation in a subsequently received packet is a suspension conclusion mode.

公开(公告)号：US11263044B2

公开(公告)日：2022-03-01

申请号：US16692856

申请日：2019-11-22

Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

Inventor： Mangesh P. Nijasure ,  Michael Mantor ,  Ashkan Hosseinzadeh Namin ,  Louis Regniere

IPC: G06F9/48 ,  G06F9/50 ,  G06T1/20 ,  G06F1/324

Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.

公开(公告)号：US11527033B2

公开(公告)日：2022-12-13

申请号：US16825600

申请日：2020-03-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Saad Arrabi ,  Vishrut Vaibhav ,  Mangesh P. Nijasure ,  Todd Martin

IPC: G06T15/00

Abstract: A graphics pipeline includes a tessellator stage having a sub-patch distributor and a plurality of tessellators. The sub-patch distributor divides an input patch into a plurality of sub-primitive groups, with the primitive group limit governing the maximum permissible size for a given group of sub-primitives to be assigned to a tessellator. The sub-patch distributor recursively identifies a plurality of regions of the input patch, with the size and number of primitives of each region based on the specified primitive group limit. The sub-patch distributor assigns different regions to different sub-patch groups and distributes the sub-patch groups among the plurality of tessellators.

公开(公告)号：US11379941B2

公开(公告)日：2022-07-05

申请号：US15415823

申请日：2017-01-25

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Todd Martin ,  Mangesh P. Nijasure ,  Randy W. Ramsey ,  Michael Mantor ,  Laurent Lefebvre

IPC: G06T1/20 ,  G06T15/00 ,  G06T15/40

Abstract: Improvements in the graphics processing pipeline are disclosed. More specifically, a new primitive shader stage performs tasks of the vertex shader stage or a domain shader stage if tessellation is enabled, a geometry shader if enabled, and a fixed function primitive assembler. The primitive shader stage is compiled by a driver from user-provided vertex or domain shader code, geometry shader code, and from code that performs functions of the primitive assembler. Moving tasks of the fixed function primitive assembler to a primitive shader that executes in programmable hardware provides many benefits, such as removal of a fixed function crossbar, removal of dedicated parameter and position buffers that are unusable in general compute mode, and other benefits.

公开(公告)号：US10388056B2

公开(公告)日：2019-08-20

申请号：US15417063

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Mangesh P. Nijasure ,  Todd Martin ,  Michael Mantor

IPC: G06T15/00 ,  G06T11/40 ,  G06F9/44

Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.

公开(公告)号：US10210650B1

公开(公告)日：2019-02-19

申请号：US15828055

申请日：2017-11-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Anirudh R. Acharya ,  Swapnil Sakharshete ,  Michael Mantor ,  Mangesh P. Nijasure ,  Todd Martin ,  Vineet Goel

IPC: G06T15/00 ,  G06T1/20 ,  G06T15/80 ,  G06F9/48 ,  G06F9/50

Abstract: Processing of non-real-time and real-time workloads is performed using discrete pipelines. A first pipeline includes a first shader and one or more fixed function hardware blocks. A second pipeline includes a second shader that is configured to emulate the at least one fixed function hardware block. First and second memory elements store first state information for the first pipeline and second state information for the second pipeline, respectively. A non-real-time workload executing in the first pipeline is preempted at a primitive boundary in response to a real-time workload being dispatched for execution in the second pipeline. The first memory element retains the first state information in response to preemption of the non-real-time workload. The first pipeline is configured to resume processing the subsequent primitive on the basis of the first state information stored in the first memory element.

公开(公告)号：US11869140B2

公开(公告)日：2024-01-09

申请号：US17234692

申请日：2021-04-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Mangesh P. Nijasure ,  Randy W. Ramsey ,  Todd Martin

IPC: G06T15/80 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T15/005

Abstract: Improvements to graphics processing pipelines are disclosed. More specifically, the vertex shader stage, which performs vertex transformations, and the hull or geometry shader stages, are combined. If tessellation is disabled and geometry shading is enabled, then the graphics processing pipeline includes a combined vertex and graphics shader stage. If tessellation is enabled, then the graphics processing pipeline includes a combined vertex and hull shader stage. If tessellation and geometry shading are both disabled, then the graphics processing pipeline does not use a combined shader stage. The combined shader stages improve efficiency by reducing the number of executing instances of shader programs and associated resources reserved.

公开(公告)号：US11715262B2

公开(公告)日：2023-08-01

申请号：US16221916

申请日：2018-12-17

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian J. Favela ,  Todd Martin ,  Mangesh P. Nijasure

IPC: G06T17/10 ,  G06T1/20 ,  G06F9/38 ,  G06T15/00

CPC classification number: G06T17/10 ,  G06F9/3877 ,  G06T1/20 ,  G06T15/005

Abstract: A method of deferred vertex attribute shading includes computing, at a graphics processing pipeline of a graphics processing unit (GPU), a plurality of vertex attributes for vertices of each primitive of a set of primitives. The plurality of vertex attributes to be computed includes a vertex position attribute and at least a first non-position attribute for each primitive. One or more primitives of the set of primitives that do not contribute to a rendered image are discarded based upon the vertex position attribute for vertices of the set of primitives. A set of surviving primitives is generated based on the culling and deferred attribute shading is performed for at least a second non-position attribute for vertices of the set of surviving primitives.

公开(公告)号：US11532066B2

公开(公告)日：2022-12-20

申请号：US17318523

申请日：2021-05-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mangesh P. Nijasure ,  Tad Litwiller ,  Todd Martin ,  Nishank Pathak

IPC: G06T1/20 ,  G06T15/00 ,  G06F9/48 ,  G06F9/38

Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.

公开(公告)号：US11010862B1

公开(公告)日：2021-05-18

申请号：US16683868

申请日：2019-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Mangesh P. Nijasure ,  Tad Litwiller ,  Todd Martin ,  Nishank Pathak

IPC: G06T1/20 ,  G06F9/38 ,  G06F9/48 ,  G06T15/00

Abstract: A graphics pipeline reduces the number of tessellation factors written to and read from a graphics memory. A hull shader stage of the graphics pipeline detects whether at least a threshold percentage of the tessellation factors for a thread group of patches are the same and, in some embodiments, whether at least the threshold percentage of the tessellation factors for a thread group of patches have a same value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that at least the threshold percentage of the tessellation factors for the thread group are the same (or, additionally, that at least the threshold percentage of the tessellation factors have a value that either indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline), the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to the graphics memory, thus reducing bandwidth and increasing efficiency of the graphics pipeline.