公开(公告)号：US20110131542A1

公开(公告)日：2011-06-02

申请号：US12634893

申请日：2009-12-10

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： G06F17/50

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US20100244934A1

公开(公告)日：2010-09-30

申请号：US12411494

申请日：2009-03-26

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Edward J. Nowak ,  Yun Shi ,  James A. Slinkman

IPC分类号： G11C5/14 ,  H01L29/06 ,  G06F17/50 ,  H01L21/762 ,  H01L21/768

CPC分类号： H01L21/84 ,  H01L21/76264 ,  H01L27/1203

摘要： At least one conductive via structure is formed from an interconnect-level metal line through a middle-of-line (MOL) dielectric layer, a shallow trench isolation structure in a top semiconductor layer, and a buried insulator layer to a bottom semiconductor layer. The shallow trench isolation structure laterally abuts at least two field effect transistors that function as a radio frequency (RF) switch. The at least one conductive via structure and the at interconnect-level metal line may provide a low resistance electrical path from the induced charge layer in a bottom semiconductor layer to electrical ground, discharging the electrical charge in the induced charge layer. The discharge of the charge in the induced charge layer thus reduces capacitive coupling between the semiconductor devices and the bottom semiconductor layer, and thus secondary coupling between components electrically disconnected by the RF switch is reduced.

摘要翻译： 至少一个导电通孔结构由通过中间线（MOL）电介质层的互连级金属线，顶部半导体层中的浅沟槽隔离结构和到半导体层的掩埋绝缘体层形成。 浅沟槽隔离结构横向邻接用作射频（RF）开关的至少两个场效应晶体管。 所述至少一个导电通孔结构和所述互连级金属线可以提供从底部半导体层中的感应电荷层到电接地的低电阻电路径，从而对感应电荷层中的电荷进行放电。 感应电荷层中的电荷的放电因此减小了半导体器件与底部半导体层之间的电容耦合，因此降低了由RF开关电断开的部件之间的二次耦合。

公开(公告)号：US20100230751A1

公开(公告)日：2010-09-16

申请号：US12538213

申请日：2009-08-10

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Alan F. Norris ,  Robert M. Rassel ,  Yun Shi

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7839 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66643 ,  H01L29/66659

摘要： A Schottky barrier diode comprises a doped guard ring having a doping of a second conductivity type in a semiconductor-on-insulator (SOI) substrate. The Schottky barrier diode further comprises a first-conductivity-type-doped semiconductor region having a doping of a first conductivity type, which is the opposite of the second conductivity type, on one side of a dummy gate electrode and a Schottky barrier structure surrounded by the doped guard ring on the other side. A Schottky barrier region may be laterally surrounded by the dummy gate electrode and the doped guard ring. The doped guard ring includes an unmetallized portion of a gate-side second-conductivity-type-doped semiconductor region having a doping of a second conductivity type. A Schottky barrier region may be laterally surrounded by a doped guard ring including a gate-side doped semiconductor region and a STI-side doped semiconductor region. Design structures for the inventive Schottky barrier diode are also provided.

摘要翻译： 肖特基势垒二极管包括在绝缘体上半导体（SOI）衬底中具有第二导电类型掺杂的掺杂保护环。 肖特基势垒二极管还包括在虚拟栅极电极的一侧上具有与第二导电类型相反的第一导电类型的掺杂的第一导电型掺杂半导体区域，以及被包围的肖特基势垒结构 另一侧的掺杂保护环。 肖特基势垒区域可以被伪栅电极和掺杂保护环横向包围。 掺杂保护环包括具有第二导电类型的掺杂的栅极侧第二导电型掺杂半导体区域的未金属化部分。 肖特基势垒区域可以由包括栅极掺杂半导体区域和STI侧掺杂半导体区域的掺杂保护环横向包围。 还提供了用于本发明的肖特基势垒二极管的设计结构。

公开(公告)号：US08021943B2

公开(公告)日：2011-09-20

申请号：US12625701

申请日：2009-11-25

申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

IPC分类号： H01L21/8238

CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

公开(公告)号：US20110124177A1

公开(公告)日：2011-05-26

申请号：US12625701

申请日：2009-11-25

申请人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

发明人： Alan B. Botula ,  BethAnn Rainey ,  Daniel S. Vanslette

IPC分类号： H01L21/762 ,  H01L21/768

CPC分类号： H01L21/743 ,  H01L21/76224 ,  H01L21/76232

摘要： A semiconductor fabrication method comprises providing a structure which includes a semiconductor substrate having a plurality of subsurface layers, the substrate comprising a top surface and the subsurface layers comprising a top subsurface layer below the top surface of the substrate. A protective material is patterned on the top surface of the device and a material removal process is performed to simultaneously form a contact trench and an isolation trench, the material removal process removing at least a portion of the top surface and the top subsurface layer such that the contact trench and the isolation trench are formed within the subsurface layer. An insulator is then formed within the isolation trench and the contact trench is lined with the insulator. The contact trench is then filled with a conductive material such that the conductive material is deposited over the insulator.

摘要翻译： 半导体制造方法包括提供包括具有多个次表面层的半导体衬底的结构，所述衬底包括顶表面，并且所述表面下层包括在所述衬底的顶表面下方的顶部表面层。 保护材料被图案化在器件的顶表面上，并且执行材料去除工艺以同时形成接触沟槽和隔离沟槽，所述材料去除工艺去除顶表面和顶部表面下层的至少一部分，使得 接触沟槽和隔离沟槽形成在地下层内。 然后在隔离沟槽内形成绝缘体，并且接触沟槽衬有绝缘体。 然后用导电材料填充接触沟槽，使得导电材料沉积在绝缘体上。

公开(公告)号：US08890246B2

公开(公告)日：2014-11-18

申请号：US13596410

申请日：2012-08-28

申请人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

发明人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

IPC分类号： H01L27/12 ,  H01L21/74 ,  H01L29/20

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L29/2003

摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

摘要翻译： 提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。 在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

公开(公告)号：US08748285B2

公开(公告)日：2014-06-10

申请号：US13280681

申请日：2011-11-28

申请人： Alan B. Botula ,  William F. Clark, Jr. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  William F. Clark, Jr. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

IPC分类号： H01L21/76

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.

摘要翻译： 半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

公开(公告)号：US20110260281A1

公开(公告)日：2011-10-27

申请号：US12764244

申请日：2010-04-21

申请人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

发明人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

IPC分类号： H01L27/12 ,  H01L23/52

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L29/2003

摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

摘要翻译： 提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。 在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

公开(公告)号：US20130134518A1

公开(公告)日：2013-05-30

申请号：US13280681

申请日：2011-11-28

申请人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

发明人： Alan B. Botula ,  William F. Clark, JR. ,  Richard A. Phelps ,  BethAnn Rainey ,  Yun Shi ,  James A. Slinkman

IPC分类号： H01L27/088 ,  H01L21/302

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A semiconductor structure includes a semiconductor-on-insulator substrate, the semiconductor-on-insulator substrate comprising a handle wafer, a buried oxide (BOX) layer on top of the handle wafer, and a top silicon layer on top of the BOX layer; and an implantation region located in the top silicon layer, the implantation region comprising a noble gas.

摘要翻译： 半导体结构包括绝缘体上半导体衬底，绝缘体上半导体衬底包括处理晶片，处理晶片顶部的掩埋氧化物（BOX）层和位于BOX层顶部的顶部硅层; 以及位于顶部硅层中的注入区域，该注入区域包括惰性气体。

公开(公告)号：US08299561B2

公开(公告)日：2012-10-30

申请号：US12764244

申请日：2010-04-21

申请人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

发明人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

IPC分类号： H01L21/70 ,  H01L23/53 ,  H01L27/12

CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L29/2003

摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

摘要翻译： 提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。 在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。