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    Tape-fixed leadframe
    4.
    发明授权
    Tape-fixed leadframe 失效
    磁带固定引线框架

    公开(公告)号：US5969412A

    公开(公告)日：1999-10-19

    申请号：US56598

    申请日：1998-04-08

    申请人： Mitsuhiro Matsutomo

    发明人： Mitsuhiro Matsutomo

    IPC分类号： H01L23/50 ,  H01L23/495 ,  H01L23/28 ,  H01L23/48 ,  H01L23/53

    CPC分类号： H01L23/49558 ,  H01L2924/0002

    摘要： A tape-fixed leadframe is provided, which prevents ion migration of metal contained in leads with a simple configuration. The leadframe is comprised of electrically-conductive lead fingers and an electrically-insulating tape for fixing the lead fingers. The tape includes an electrically-insulating base film and an electrically-insulating adhesive layer formed on a surface of the base film. The adhesive layer of the tape is adhered to the lead fingers, thereby fixing the lead fingers at their original positions. The adhesive layer has protruded parts located at respective sides of each of the lead fingers, intervening parts between two adjoining ones of the protruded parts, and depressed parts opposite to the lead fingers. The protruded parts are thicker than the intervening parts. The depressed parts are thinner than the intervening parts. Ionized atoms of a metal contained in the lead fingers are trapped by the protruded parts and as a result, ion migration of the metal is prevented from occurring with a simple configuration.

    摘要翻译： 提供了一种带状固定的引线框架，其以简单的配置防止引线中包含的金属的离子迁移。 引线框由导电引线指和用于固定引线指的电绝缘带构成。 带包括电绝缘基膜和形成在基膜表面上的电绝缘粘合剂层。 带的粘合剂层粘附到引导指，从而将引线指固定在其原始位置。 粘合剂层具有位于每个引线指的相应侧的突出部分，两个相邻的突出部分之间的中间部分和与引线指相对的凹陷部分。 突出部分比中间部分厚。 凹陷部分比中间部分薄。 包含在引线指中的金属的电离原子被突出部分捕获，结果，以简单的结构防止金属的离子迁移发生。

    Shielding for high-voltage semiconductor-on-insulator devices
    5.
    发明授权
    Shielding for high-voltage semiconductor-on-insulator devices 有权
    高压绝缘体上半导体器件屏蔽

    公开(公告)号：US08299561B2

    公开(公告)日：2012-10-30

    申请号：US12764244

    申请日：2010-04-21

    申请人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

    发明人： Alan B. Botula ,  Beth Ann Rainey ,  Yun Shi

    IPC分类号： H01L21/70 ,  H01L23/53 ,  H01L27/12

    CPC分类号： H01L27/1203 ,  H01L21/743 ,  H01L29/2003

    摘要： Integrated circuits having doped bands in a substrate and beneath high-voltage semiconductor-on-insulator (SOI) devices are provided. In one embodiment, the invention provides an integrated circuit comprising: a semiconductor-on-insulator (SOI) wafer including: a substrate; a buried oxide (BOX) layer atop the substrate; and a semiconductor layer atop the BOX layer; a plurality of high voltage (HV) devices connected in series within the semiconductor layer; a doped band within the substrate and below a first of the plurality of HV devices; and a contact extending from the semiconductor layer and through the BOX layer to the doped band.

    摘要翻译： 提供了在衬底中和在绝缘体上绝缘体（SOI）器件上的高压绝缘体（SOI）器件下面具有掺杂带的集成电路。 在一个实施例中，本发明提供一种集成电路，包括：绝缘体上半导体（SOI）晶片，其包括：基板; 衬底上的掩埋氧化物（BOX）层; 以及位于BOX层顶部的半导体层; 在半导体层内串联连接的多个高压（HV）器件; 在所述衬底内并在所述多个HV器件中的第一个之下的掺杂带; 以及从半导体层和BOX层延伸到掺杂带的接触。

    Structure for a stacked power clamp having a BigFET gate pull-up circuit
    6.
    发明授权
    Structure for a stacked power clamp having a BigFET gate pull-up circuit 有权
    具有BigFET栅极上拉电路的堆叠式功率钳的结构

    公开(公告)号：US08010927B2

    公开(公告)日：2011-08-30

    申请号：US12127245

    申请日：2008-05-27

    申请人： Robert J. Gauthier, Jr. ,  Junjun Li

    发明人： Robert J. Gauthier, Jr. ,  Junjun Li

    IPC分类号： G06F17/50 ,  G06F9/45 ,  G06F9/455 ,  H01L23/53 ,  H01L23/62 ,  H01L29/66

    CPC分类号： G06F17/5045 ,  H01L27/0285 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Design structure for an electrostatic discharge (ESD) protection circuit for protecting an integrated circuit chip from an ESD event. The design structure for the ESD protection circuit includes a stack of BigFETs, a BigFET gate driver for driving the gates of the BigFETs, and a trigger for triggering the BigFET gate driver to drive the gates of the BigFETs in response to an ESD event. The BigFET gate driver includes gate pull-up circuitry for pulling up the gate of a lower one of the BigFETs. The gate pull-up circuitry is configured so as to obviate the need for a diffusion contact between the stacked BigFETs, resulting in a significant savings in terms of the chip area needed to implement the ESD protection circuit.

    摘要翻译： 用于保护集成电路芯片免受ESD事件的静电放电（ESD）保护电路的设计结构。 ESD保护电路的设计结构包括一堆BigFET，用于驱动BigFET栅极的BigFET栅极驱动器，以及用于触发BigFET栅极驱动器以响应于ESD事件来驱动BigFET栅极的触发器。 BigFET栅极驱动器包括用于拉低下一个BigFET的栅极的栅极上拉电路。 栅极上拉电路被配置为消除对堆叠的BigFET之间的扩散接触的需要，导致实现ESD保护电路所需的芯片面积的显着节省。

    Semiconductor chip package with interconnect layers and routing and testing methods
    8.
    发明授权
    Semiconductor chip package with interconnect layers and routing and testing methods 失效
    具有互连层和路由和测试方法的半导体芯片封装

    公开(公告)号：US5777383A

    公开(公告)日：1998-07-07

    申请号：US647344

    申请日：1996-05-09

    申请人： Mark P. Stager ,  Abraham F. Yee ,  Gobi R. Padmanabhan

    发明人： Mark P. Stager ,  Abraham F. Yee ,  Gobi R. Padmanabhan

    IPC分类号： G01R31/28 ,  H01L23/498 ,  H01L23/538 ,  H01L23/53 ,  H01L23/12 ,  H01L25/10

    CPC分类号： G06F17/5068 ,  G01R31/2884 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5382 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01079 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/3025

    摘要： A package for a semiconductor chip is provided which incorporates a plurality of levels of interconnect--conductive layers within the package which selectively direct signals to and from pins of the die and/or the pins of the package. A single general purpose chip may thus be fabricated in large quantities with the interconnect of the package used to define the specific purpose, functionality and pinout of the final device. Similarly, a standard package may be built to work with a large class of different chips and only the interconnect layers in the package need to be modified to allow the package to work with each different chip. In a second aspect of the invention, one or more layers of interconnect in the package may contain active electronic components which may be connected to nodes of the chip through the interconnect of the package and through the pins of the die. Accordingly, devices which are difficult or impossible to incorporate into a semiconductor die may be incorporated into a single package along with the die. In a third aspect of the invention, a method of integrated circuit design includes using a conventional CAD design tool software package to design not only the integrated circuit, but also variable circuit elements (such as interconnect and electronic components) embedded in the chip package. In a fourth aspect of the invention, a testing methodology for wafer die subcomponents is provided.

    摘要翻译： 提供了一种用于半导体芯片的封装件，其在封装内包括多个级别的互连导电层，其选择性地将信号引导到管芯的引脚和/或封装的引脚。 因此，可以大量地制造单个通用芯片，其中封装的互连用于限定最终器件的特定目的，功能和引脚排列。 类似地，可以构建标准封装以与大类不同的芯片一起工作，并且仅需要修改封装中的互连层以允许封装与每个不同的芯片一起工作。 在本发明的第二方面中，封装中的一个或多个互连层可以包含有源电子部件，其可以通过封装的互连和芯片的引脚连接到芯片的节点。 因此，难以或不可能并入到半导体管芯中的器件可以与管芯一起并入单个封装中。 在本发明的第三方面中，集成电路设计的方法包括使用传统的CAD设计工具软件包来设计不仅集成电路，而且设计嵌入在芯片封装中的可变电路元件（例如互连和电子元件）。 在本发明的第四方面，提供了一种用于晶片模具子部件的测试方法。

    Double-packaged multi-chip semiconductor module
    9.
    发明授权
    Double-packaged multi-chip semiconductor module 失效
    双封装多芯片半导体模块

    公开(公告)号：US07259450B2

    公开(公告)日：2007-08-21

    申请号：US10423122

    申请日：2003-04-25

    申请人： Alan G. Wood ,  Eugene H. Cloud ,  Larry D. Kinsman

    发明人： Alan G. Wood ,  Eugene H. Cloud ,  Larry D. Kinsman

    IPC分类号： H01L23/02 ,  H01L23/12 ,  H01L23/53 ,  H01L23/43

    CPC分类号： H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/00

    摘要： A plurality of semiconductor die is packaged into one component. The inventive design comprises devices which have been singularized, packaged and thoroughly tested for functionality and adherence to required specifications. A plurality of packaged devices is then received by a housing. The conductive leads of the packaged devices are electrically coupled with pads manufactured into the housing. These pads are connected to traces within the housing, which terminate externally to the housing. Input/output leads are then electrically coupled with the traces, or are coupled with the traces as the housing is manufactured. The input/output leads provide means for connecting the housing with the electronic device or system into which it is installed. A lid received by the housing hermetically seals the packaged die in the housing, and prevents moisture or other contaminants which may impede the proper functionality of the die from entering the housing.

    摘要翻译： 将多个半导体管芯封装成一个部件。 本发明的设计包括已经被单一化，封装和彻底测试的功能和遵守所需规格的装置。 然后，多个封装的装置被壳体接收。 封装器件的导电引线与制造在外壳中的焊盘电耦合。 这些焊盘连接到壳体内的迹线，外壳上的迹线终止。 然后，输入/输出引线与迹线电耦合，或者当制造外壳时与引线耦合。 输入/输出引线提供用于将壳体与其所安装的电子设备或系统连接的装置。 由壳体容纳的盖子将封装的模具密封在壳体中，并且防止可能妨碍模具的正常功能的水分或其它污染物进入壳体。