公开(公告)号：US09343139B2

公开(公告)日：2016-05-17

申请号：US14807982

申请日：2015-07-24

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C7/00 ,  G11C11/419 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

公开(公告)号：US20150332754A1

公开(公告)日：2015-11-19

申请号：US14807982

申请日：2015-07-24

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C11/417 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.

Abstract translation: 在一个实施例中，集成电路包括由第一电源电压提供的至少一个逻辑电路和耦合到逻辑电路并由第二电源电压提供的至少一个存储器电路。 即使在使用期间第一电源电压小于第二电源电压，存储器电路被配置为响应于逻辑电路被读取和写入。 在另一个实施例中，一种方法包括：读取存储单元的逻辑电路，由第一电源电压提供的逻辑电路; 并且所述存储单元响应于所读取的使用参考于所述第一电源电压的信号，其中所述存储单元被提供在使用期间大于所述第一电源电压的第二电源电压。

公开(公告)号：US20150253836A1

公开(公告)日：2015-09-10

申请号：US14200216

申请日：2014-03-07

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract translation: 在一个实施例中，集成电路包括组件（例如处理器）和控制电路的多个实例。 这些实例可以被配置为以各种模式操作。 一些模式不能在电源上呈现最坏的负载。 控制电路可以被配置为监视实例并检测实例正在操作的模式。 基于监视，控制电路可以请求恢复在实例中为最坏情况条件建立的电压余量的一部分。 如果实例要改变模式，则它们可以被配置为从控制电路请求模式改变。 如果模式改变导致当前电源电压幅度的增加（例如，恢复一些恢复的电压余量），则控制电路可以在授予模式改变之前导致恢复并允许其恢复。

公开(公告)号：US20130182493A1

公开(公告)日：2013-07-18

申请号：US13787894

申请日：2013-03-07

Applicant: Apple Inc.

Inventor： Brian J. Campbell ,  Vincent R. von Kaenel ,  Daniel C. Murray ,  Gregory S. Scott ,  Sribalan Santhanam

IPC: G11C7/12 ,  G11C7/00

CPC classification number: G11C11/419 ,  G11C5/143 ,  G11C7/00 ,  G11C7/12 ,  G11C8/08 ,  G11C11/417 ,  H03K3/35613 ,  H03K19/018528

Abstract: In one embodiment, an integrated circuit includes at least one logic circuit supplied by a first supply voltage and at least one memory circuit coupled to the logic circuit and supplied by a second supply voltage. The memory circuit is configured to be read and written responsive to the logic circuit even if the first supply voltage is less than the second supply voltage during use. In another embodiment, a method includes a logic circuit reading a memory cell, the logic circuit supplied by a first supply voltage; and the memory cell responding to the read using signals that are referenced to the first supply voltage, wherein the memory cell is supplied with a second supply voltage that is greater than the first supply voltage during use.