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公开(公告)号:US11925079B2
公开(公告)日:2024-03-05
申请号:US17364659
申请日:2021-06-30
Inventor: Yuanyou Qiu , Yao Huang , Weiyun Huang , Binyan Wang , Zhi Wang
IPC: H01L21/00 , H10K50/822 , H10K59/122 , H10K59/131
CPC classification number: H10K59/131 , H10K50/822 , H10K59/122
Abstract: A display panel, includes: a substrate; and a plurality of OLED devices disposed on the substrate, each of which includes an anode and a light-emitting layer arranged in stack; further includes a patterned area, the patterned area comprising at least one cathode group, each of which includes a plurality of cathodes arranged at intervals, and an orthographic projection of each of the plurality of cathodes on the substrate at least covers an orthographic projection of the light-emitting layer of one of the plurality of OLED devices on the substrate; and for each of the at least one cathode group, the display panel further includes a plurality of first wirings electrically connected to the plurality of cathodes in one-to-one correspondence and a second wiring electrically connected to the plurality of first wirings and electrically connected to a VSS signal line. A display device is further provided.
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32.
公开(公告)号:US11817460B2
公开(公告)日:2023-11-14
申请号:US17263748
申请日:2020-03-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Chao Luo , Feng Guan , Zhi Wang , Jianhua Du , Yang Lv , Zhaohui Qiang , Chao Li
IPC: H01L27/12 , H01L29/66 , H01L29/786
CPC classification number: H01L27/1237 , H01L27/1222 , H01L27/1285 , H01L29/66477 , H01L29/66765 , H01L29/78669 , H01L29/78678
Abstract: A thin film transistor includes a gate, a gate insulating layer, an active layer, an ionized amorphous silicon layer, a source and a drain. The gate insulating layer covers the gate. The active layer is disposed on a side of the gate insulating layer away from the gate. The ionized amorphous silicon layer is disposed on a side of the active layer away from the gate, and the ionized amorphous silicon layer is in contact with the gate insulating layer. The source and the drain are disposed on a side of the ionized amorphous silicon layer away from the gate insulating layer, and the source and the drain are coupled to the active layer through the ionized amorphous silicon layer.
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公开(公告)号:US11251208B2
公开(公告)日:2022-02-15
申请号:US16642734
申请日:2019-03-18
Applicant: BOE Technology Group Co., Ltd.
Inventor: Chao Li , Jianhua Du , Feng Guan , Zhaohui Qiang , Zhi Wang , Yupeng Gao , Yang Lv
IPC: H01L27/144 , H01L27/12 , H01L31/0352 , H01L31/105 , H01L31/18
Abstract: A photosensor includes a base substrate; an insulating layer on the base substrate; and a photodiode including a semiconductor junction on a side of the insulating layer away from the base substrate. The semiconductor junction includes a first polarity semiconductor layer, an intrinsic semiconductor layer, and a second polarity semiconductor layer, stacked on the insulating layer. The second polarity semiconductor layer encapsulates a lateral surface of the intrinsic semiconductor layer.
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公开(公告)号:US20210382601A1
公开(公告)日:2021-12-09
申请号:US16332240
申请日:2018-07-11
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Shengji Yang , Xue Dong , Xiaochuan Chen , Hui Wang , Yanming Wang , Pengcheng Lu , Wei Liu , Zhi Wang , Lei Wang , Huijuan Wang
Abstract: A display panel includes a touch electrode layer (4). The touch electrode layer (4) may include a plurality of touch electrodes (41). Each of the plurality of the touch electronics (41) may be insulated from one another. A shape of each of the plurality of the touch electronics (41) may be configured to determine a distance of a touch position on one of the plurality of the touch electrodes (41) to a geometric center of the touch electrode layer (4) based on a change of a capacitance of each of the plurality of the touch electrodes (41).
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公开(公告)号:US20210151476A1
公开(公告)日:2021-05-20
申请号:US16642734
申请日:2019-03-18
Applicant: BOE Technology Group Co., Ltd.
Inventor: Chao Li , Jianhua Du , Feng Guan , Zhaohui Qiang , Zhi Wang , Yupeng Gao , Yang Lv
IPC: H01L27/144 , H01L31/105 , H01L31/0352 , H01L27/12 , H01L31/18
Abstract: A photosensor includes a base substrate; an insulating layer on the base substrate; and a photodiode including a semiconductor junction on a side of the insulating layer away from the base substrate. The semiconductor junction includes a first polarity semiconductor layer, an intrinsic semiconductor layer, and a second polarity semiconductor layer, stacked on the insulating layer. The second polarity semiconductor layer encapsulates a lateral surface of the intrinsic semiconductor layer.
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公开(公告)号:US20200251327A1
公开(公告)日:2020-08-06
申请号:US16569311
申请日:2019-09-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
IPC: H01L21/02 , H01L23/544 , H01L21/306 , H01L27/12 , B23K26/06 , B23K26/354
Abstract: A laser annealing process of a drive backplane includes: providing a mask, which has a light transmission area; and sequentially moving the mask to cover different areas of an amorphous silicon layer of the drive backplane, and annealing the amorphous silicon layer exposed in the light transmission area to form a poly-silicon pattern.
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37.
公开(公告)号:US20190148461A1
公开(公告)日:2019-05-16
申请号:US16130156
申请日:2018-09-13
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor: Zhi Wang , Shengji Yang , Pengcheng Lu
Abstract: The disclosure provides a method for manufacturing cathode isolation retaining walls, display panel and manufacturing method thereof. A method for manufacturing a cathode isolation retaining wall, including exposing a first photoresist layer formed on an anode layer to obtain a first isolation retaining wall portion. The method includes forming a second photoresist layer on a side of the first photoresist layer away from the anode layer. After exposing the second photoresist layer, a second isolation retaining wall portion at least partially stacked with the first isolation retaining wall portion is obtained. The method includes developing the first photoresist layer and the second photoresist layer to obtain a cathode isolation retaining wall composed of the first isolation retaining wall portion and the second isolation retaining wall portion.
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