-
公开(公告)号：US11774790B2
公开(公告)日：2023-10-03
申请号：US17846074
申请日：2022-06-22
Inventor： Yifu Chen , Seungmin Lee , Yanping Liao , Lei Guo , Yingying Qu , Zhe Li , Liangliang Jiang , Lifeng Lin , Lan Xin , Zhihua Sun
IPC: G02F1/1333 , G02F1/1335 , G02F1/13357 , G02F1/1339
CPC classification number: G02F1/133308 , G02F1/1339 , G02F1/133514 , G02F1/133602
Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.
-
公开(公告)号：US20210223647A1
公开(公告)日：2021-07-22
申请号：US16629313
申请日：2019-08-27
Inventor： Xiaoyuan Wang , Wu Wang , Yan Fang , Ruilin Bi , Yajie Bai , Yujie Gao , Seungmin Lee
IPC: G02F1/1362 , G02F1/1368
Abstract: An array substrate includes a base substrate; a data line and a common electrode line on the base substrate; and a first gate line and a second gate line on the base substrate, wherein both the first gate line and the second gate line cross both the data line and the common electrode line to define a sub-pixel. The sub-pixel includes: a pixel electrode; a common electrode; and an insulating layer between the pixel electrode and the common electrode. The common electrode includes a plurality of slits, and the slits extend in the same direction as the data line. The slits include a first slit close to the data line, the pixel electrode includes a first side surface close to the data line, and an orthographic projection of the first side surface on the base substrate is located within an orthographic projection of the first slit on the base substrate.
-
公开(公告)号：US09864222B2
公开(公告)日：2018-01-09
申请号：US14777837
申请日：2015-04-17
Inventor： Xibin Shao , Yingying Qu , Honglin Zhang , Hebin Zhao , Seungmin Lee , Dan Wang , Xiang Li
IPC: G09G3/36 , G02F1/1333 , G09F9/30 , H05K7/14
CPC classification number: G02F1/133308 , G02F2001/133314 , G02F2001/133325 , G02F2201/56 , G09F9/301 , H05K7/1417
Abstract: A curved display panel, a curved display device, and a method for fabricating the same are disclosed. Both the light output face and the light input face of the curved display panel are continuously curved surfaces. The curved display panel with a continuously curved surface has a bending degree which is closer to the natural bending degree of a liquid crystal panel, so that a relatively small stress is generated on the curved display panel, and the problem of serious peripheral light leakage caused by deformation of the curved display panel is alleviated. Besides, since the curvature radius of each point on the continuously curved surface changes slowly, the problem of serious peripheral light leakage caused by deformation of the curved display panel is alleviated, the complexity of the fabricating process is reduced, the fabricating process is simplified, and the production of the product is improved.
-
公开(公告)号：US09734784B2
公开(公告)日：2017-08-15
申请号：US15136206
申请日：2016-04-22
Inventor： Baoyu Liu , Zhihua Sun , Seungmin Lee , Honglin Zhang , Weichao Ma , Jianming Wang , Shulin Yao , Xu Zhang
CPC classification number: G09G3/3674 , G05F3/16 , G09G3/3696 , G09G2300/0852 , G09G2300/0871 , G09G2310/0248 , G09G2310/0286 , G09G2310/0289 , G09G2330/026 , G11C19/184
Abstract: The present invention provides a voltage output device, which comprises a direct-current power supply, a reference level input terminal, a predetermined level output terminal, a voltage regulation module and a control signal generation module, the control signal generation module comprises a control signal generation unit, the voltage regulation module comprises a plurality of storage capacitors, wherein the control signal generation unit can send a charging control signal to the voltage regulation module in a charging stage of the voltage output device, and send an operation control signal to the voltage regulation module in an operating stage of the voltage output device. The present invention further provides a gate driving circuit and a display apparatus. With the voltage output device provided by the present invention, a high-level voltage that is high enough and/or a low-level voltage that is low enough can be outputted, thereby satisfying specific application requirements.
-
公开(公告)号：US20170039947A1
公开(公告)日：2017-02-09
申请号：US14913325
申请日：2015-08-13
Inventor： Xu Zhang , Zhihua Sun , Jianming Wang , Weichao Ma , Seungmin Lee , Honglin Zhang , Zhihao Zhang
IPC: G09G3/3258
CPC classification number: G09G3/3258 , G09G3/3233 , G09G2300/0439 , G09G2300/0819 , G09G2300/0852 , G09G2300/0861 , G09G2310/08 , G09G2320/0223 , G09G2320/043
Abstract: The present invention provides a pixel circuit and a driving method thereof, as well as a display device. The pixel circuit comprises a drive transistor and a first energy storage element, a source of the drive transistor being connected with a first end of the first energy storage element. The pixel circuit further comprises a driving module, and has a reset voltage input terminal, a data voltage input terminal, a working voltage input terminal and a plurality of control signal input terminals. The pixel circuit provided by the present invention can prevent the driving current flowing through the electroluminescent unit from being influenced by the turn-on threshold value of the corresponding drive transistor, thereby solving the problem of non-uniform display brightness caused by drift of the turn-on threshold value of the drive transistor thoroughly.
Abstract translation: 本发明提供一种像素电路及其驱动方法以及显示装置。 像素电路包括驱动晶体管和第一能量存储元件，驱动晶体管的源极与第一能量存储元件的第一端连接。 像素电路还包括驱动模块，并且具有复位电压输入端子，数据电压输入端子，工作电压输入端子和多个控制信号输入端子。 本发明提供的像素电路可以防止流过电致发光单元的驱动电流受到相应的驱动晶体管的导通阈值的影响，从而解决了由转弯漂移引起的不均匀显示亮度的问题 - 驱动晶体管的阈值彻底。
-
Patent Agency Ranking
公开(公告)号：US20150212361A1
公开(公告)日：2015-07-30
申请号：US14418144
申请日：2014-06-20
Inventor： Feng Zhao , Dan Wang , Seungmin Lee , Bin Zou , Junjie Guo , Yutao Hao
IPC: G02F1/1333 , G02F1/1335
CPC classification number: G02F1/133308 , G02F2001/133317 , G02F2201/465
Abstract: The present disclosure provides a bezel-free display device, including: a display panel including a display surface and a back surface opposite to the display surface; a panel connector, one end of which is secured onto a peripheral region of the back surface, and the other end of which is provided with a first support surface, a first snap-on member being provided on the first support surface; and a backlight module including a back plate and a sealant both arranged at a side of the back surface, the sealant being secured onto a periphery of the back plate and arranged at a position corresponding to the panel connector, one end of the sealant adjacent to the display panel being provided with a second support surface cooperating with the first support surface, a second snap-on member cooperating with the first snap-on member being provided on the second support surface.
Abstract translation: 本公开提供了一种无挡边显示装置，包括：显示面板，包括显示面和与显示面相对的背面; 面板连接器，其一端固定在后表面的周边区域，另一端设有第一支撑表面，第一卡扣元件设置在第一支撑表面上; 以及背面模块，其包括背板和密封剂，两者均布置在所述背面的一侧，所述密封剂被固定在所述背板的周边上并且布置在与所述面板连接器相对应的位置处，所述密封件的一端邻近 显示面板设置有与第一支撑表面协作的第二支撑表面，与第一卡扣构件配合的第二卡扣构件设置在第二支撑表面上。
-
公开(公告)号：US12230184B2
公开(公告)日：2025-02-18
申请号：US17634733
申请日：2021-03-29
Inventor： Qiujie Su , Yingmeng Miao , Dongchuan Chen , Yanping Liao , Seungmin Lee , Xibin Shao , Xiaofeng Yin
Abstract: At least one chip group and a group of first PLG wirings corresponding to each of the chip groups are disposed in a first bonding area, each of the chip groups includes at least two groups of chip units, each group of the chip units includes at least one gate drive chip, each group of the first PLG wirings includes a first wiring and at least one second wiring; power pins of any two adjacent gate drive chips are connected by the first wiring, each of the second wirings surrounds and passes through each of the gate drive chips, the first wirings connected with the power pin of the last gate drive chip in the previous group of the chip units and any of the second wirings, are parallelly connected with the power pin of the first gate drive chip in the next group of the chip units.
-
公开(公告)号：US12106694B2
公开(公告)日：2024-10-01
申请号：US18338516
申请日：2023-06-21
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/08 , G09G2310/0243 , G09G2310/0267 , G09G2310/0286 , G09G2310/08
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
-
公开(公告)号：US20230351936A1
公开(公告)日：2023-11-02
申请号：US18338516
申请日：2023-06-21
Inventor： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC classification number: G09G3/20 , G11C19/28 , G09G2310/0267 , G09G2300/0408 , G09G2310/08 , G09G2300/08 , G09G2310/0243 , G09G2310/0286
Abstract: There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
-
公开(公告)号：US11774789B2
公开(公告)日：2023-10-03
申请号：US16959286
申请日：2019-08-20
Inventor： Yifu Chen , Seungmin Lee , Yanping Liao , Lei Guo , Yingying Qu , Zhe Li , Liangliang Jiang , Lifeng Lin , Lan Xin , Zhihua Sun
IPC: G02F1/1333 , G02F1/1335 , G02F1/13357 , G02F1/1339
CPC classification number: G02F1/133308 , G02F1/1339 , G02F1/133514 , G02F1/133602
Abstract: Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.
-
-
-
-
-
-
-
-
-
Search Results
46
records
(took 0.025 seconds)
