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公开(公告)号：US12106694B2
公开(公告)日：2024-10-01
申请号：US18338516
申请日：2023-06-21
发明人： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC分类号： G09G3/20 , G11C19/28 , G09G2300/0408 , G09G2300/08 , G09G2310/0243 , G09G2310/0267 , G09G2310/0286 , G09G2310/08
摘要： There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US20230351936A1
公开(公告)日：2023-11-02
申请号：US18338516
申请日：2023-06-21
发明人： Yingmeng Miao , Changcheng Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
CPC分类号： G09G3/20 , G11C19/28 , G09G2310/0267 , G09G2300/0408 , G09G2310/08 , G09G2300/08 , G09G2310/0243 , G09G2310/0286
摘要： There is provided a gate driving circuit comprising N first shift registers arranged alternately with N second shift registers. An input signal terminal of an n-th stage of first shift register is coupled to an output signal terminal of an (n−i)-th stage of first shift register, and a reset signal terminal of the n-th stage of first shift register is coupled to an output signal terminal of an (n+j)-th stage of first shift register. Input signal terminal and reset signal terminal of n-th stage of second shift register are coupled to output signal terminals of (n−i)-th and (n+j)-th stages of second shift registers respectively. K=6, i=3, and j=4. Reset signal terminals of (N−j+1)-th to N-th stages of first shift registers and reset signal terminals of (N−j+1)-th to N-th stages of second shift registers are configured to receive a total reset signal.
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公开(公告)号：US11774789B2
公开(公告)日：2023-10-03
申请号：US16959286
申请日：2019-08-20
发明人： Yifu Chen , Seungmin Lee , Yanping Liao , Lei Guo , Yingying Qu , Zhe Li , Liangliang Jiang , Lifeng Lin , Lan Xin , Zhihua Sun
IPC分类号： G02F1/1333 , G02F1/1335 , G02F1/13357 , G02F1/1339
CPC分类号： G02F1/133308 , G02F1/1339 , G02F1/133514 , G02F1/133602
摘要： Embodiments of the present disclosure provide a display panel and a display device. The display panel includes: a first substrate; at least one underlaying structure, arranged on the first substrate and in a non-display region of at least one side of a display region of the display panel; and at least one supporting structure, arranged on one side, facing away from the first substrate, of the at least one underlaying structure, where an orthographic projection of the supporting structure on the first substrate is within a range of an orthographic projection of the underlaying structure on the first substrate.
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公开(公告)号：US11568778B2
公开(公告)日：2023-01-31
申请号：US17351638
申请日：2021-06-18
发明人： Yingmeng Miao , Changchen Liu , Zhihua Sun , Yanping Liao , Seungmin Lee , Xibin Shao , Cong Wang , Feng Qu
摘要： According to the embodiments of the present disclosure, there is provided gate driving circuit comprising 2N stages of shift registers, the 2N stages of shift registers comprising N first shift registers arranged alternately with N second shift registers, wherein the N first shift registers are cascaded-coupled as N stages of first shift registers, and are configured to generate N first output signals under control of K first clock signals; and wherein the N second shift registers are cascaded-coupled as N stages of second shift registers, and are configured to generate N second output signals under a control of K second clock signals, wherein K and N are both integers greater than 1, and K≤N.
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公开(公告)号：US11455929B2
公开(公告)日：2022-09-27
申请号：US17458171
申请日：2021-08-26
发明人： Zhihua Sun , Yinlong Zhang , Senwang Li , Yanping Liao , Xibin Shao , Feng Qu
IPC分类号： G09G3/20
摘要： The present disclosure discloses a driving method and apparatus of a display panel. When the display panel is driven to display a (2k−1)th image, only display data, corresponding to pixels of one row group, in image data of a kth display frame of a plurality of display frames are transmitted to a driver chip in the display panel, and a data size transmitted may be reduced. When the display panel is driven to display a (2k)th image, display data, corresponding to pixels of another row group, in the image data of the kth display frame are transmitted to the driver chip in the display panel, and the data size transmitted may also be reduced.
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公开(公告)号：US10650735B2
公开(公告)日：2020-05-12
申请号：US16168958
申请日：2018-10-24
发明人： Jituo Tang , Guohuo Su , Shulin Yao , Zhihua Sun , Yinlong Zhang , Xu Zhang , Ning Zhang , Wenpeng Ma
IPC分类号： G09G3/3208 , H02M3/07
摘要： A charge pump, a voltage control method for the charge pump, and a display device are provided. The charge pump includes a voltage output end and a first step-up circuitry. The first step-up circuitry includes a first energy storage unit, a second energy storage unit, a first input control unit, a first voltage application control unit, a first output control unit and a first charging path control unit. The first voltage application control unit is configured to enable a first end of the first energy storage unit to be electrically connected to, or electrically disconnected from, a first voltage end, and enable a first end of the second energy storage unit to be electrically connected to, or electrically disconnected from, a second voltage end.
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7.发明申请公开(公告)号：US20180226959A1
公开(公告)日：2018-08-09
申请号：US15710317
申请日：2017-09-20
发明人： Guohuo Su , Zhihua Sun , Xu Zhang , Zhihao Zhang , Guangquan He , Song Liu
CPC分类号： H03K5/15093 , G09G3/20 , G09G2310/0275 , G09G2310/0286 , H03K2005/00241
摘要： Embodiments of the present disclosure provide a clock signal transmission circuit, a driving method thereof, a gate driving circuit, and a display device. The clock signal transmission circuit includes an input circuit, a pull-up circuit, a reset circuit, a pull-down control circuit, a pull-down circuit, and a pull-up holding circuit. According to an embodiment of the present disclosure, the clock signal source can be disconnected from each shift register unit in the gate driving circuit before a screen is displayed, preventing malfunctions of the gate driving circuit caused by an undesired high voltage on the clock signal line.
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公开(公告)号：US09971219B1
公开(公告)日：2018-05-15
申请号：US15704170
申请日：2017-09-14
发明人： Deqiang Liu , Feifei Wang , Zhihua Sun , Yujie Gao , Honglin Zhang , Hebin Zhao
IPC分类号： G02F1/1362
CPC分类号： G02F1/136286 , G02F1/1339 , G02F1/136227 , G02F2001/136222 , G02F2201/50
摘要： Embodiments of the present disclosure provide an array substrate, a color filter substrate and a display panel. The array substrate includes: a base substrate; gate lines and data lines provided above the base substrate in a cross arrangement; and a plurality of pixel units defined by the gate lines and the data lines, each pixel unit including a pixel region and a non-pixel region. At least a portion of the gate line is located in the non-pixel region, a blocking wall region is formed in the non-pixel region and located between the portion of the gate line located in the non-pixel region and the pixel region, and a blocking wall structure for blocking movement of a spacer from the non-pixel region to the pixel region is formed in the blocking wall region.
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公开(公告)号：US09646554B2
公开(公告)日：2017-05-09
申请号：US14430016
申请日：2014-05-16
发明人： Baoyu Liu , Liang Zhang , Yizhen Xu , Zhihua Sun
IPC分类号： G09G3/36 , H03K19/0185 , G09G3/20 , H03K19/0175
CPC分类号： G09G3/3648 , G09G3/20 , G09G3/3696 , G09G2300/0426 , G09G2310/0267 , G09G2310/0289 , H03K19/017509 , H03K19/018528
摘要： Provided are a level shift circuit, a gate driving circuit and a display apparatus. The level shift circuit includes: a third to a sixth transistor, sources and gates thereof being connected to a DC power source and an offset voltage terminal respectively; a seventh transistor, source and gate thereof being connected to a reference ground and the offset voltage terminal respectively; and a first to a second transistor, gates and sources thereof being connected to an input signal terminal and drain of seventh transistor respectively, wherein drains of third and fifth transistors are connected as a first output terminal which is connected to drain of the first transistor, drains of fourth and sixth transistors are connected as a second output terminal which is connected to drain of the second transistor. Common-mode voltage of two output terminals of the level shift circuit with respect to the reference ground is not reduced.
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公开(公告)号：US12107073B2
公开(公告)日：2024-10-01
申请号：US17429929
申请日：2020-10-27
发明人： Zhihua Sun , Yanping Liao , Seungmin Lee , Qiujie Su , Feng Qu , Yingmeng Miao , Xibin Shao
IPC分类号： H01L25/065 , H01L25/00 , H01L23/12
CPC分类号： H01L25/0655 , H01L25/50 , H01L23/12
摘要： A display device and a method for bonding the display device are provided. The display device includes a display panel and a plurality of chip on films. The plurality of chip on films are arranged along a first edge of the display panel, and are divided into a plurality of groups of chip on films, and each group of chip on films includes at least two chip on films, and is bonded to the display panel through a same anisotropic conductive film.
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