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公开(公告)号：US10274682B2
公开(公告)日：2019-04-30
申请号：US15439748
申请日：2017-02-22
申请人： Ciena Corporation
摘要： A system for providing optical connections that may include an optical grating structure and an optical waveguide coupled to the optical grating structure. The optical grating structure may be configured to receive an optical wave, through an interposer, from an optical source. The optical grating structure may be configured to transform the optical wave into a predetermined electromagnetic propagation mode.
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公开(公告)号：US20190097730A1
公开(公告)日：2019-03-28
申请号：US16199745
申请日：2018-11-26
申请人： Ciena Corporation
IPC分类号： H04B10/40
摘要： A storage system includes a connection to one or more optical transceivers, each having one or more Field Programmable Gate Arrays (FPGAs); and a processor and memory storing instructions that, when executed, cause the processor to receive a request for one or more applications for a specific optical transceiver of the one or more optical transceivers, and provide the one or more applications to the specific optical transceiver, wherein the one or more applications are utilized in the specific optical transceiver to dynamically configure digital functionality in its one or more FPGAs for operation in an optical network.
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公开(公告)号：US10239749B2
公开(公告)日：2019-03-26
申请号：US15834185
申请日：2017-12-07
申请人： Ciena Corporation
摘要： An electrical cross-point switch N inputs, each at least 10 Gbps, connected to input transmission lines; M outputs, each at least 10 Gbps, connected to output transmission lines; at least two Radio Frequency (RF) Microelectromechanical systems (MEMS) switches selectively interconnecting each input transmission line and each output transmission line; and control and addressing circuitry configured to selectively control interconnection of each input transmission line and each output transmission line via the at least two RF MEMS switches. The at least two RF MEMS switches can be embedded in each input transmission line and each output transmission line. The input transmission lines and the output transmission lines can each be partially shielded microwave transmission lines.
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公开(公告)号：US20170353246A1
公开(公告)日：2017-12-07
申请号：US15175118
申请日：2016-06-07
申请人： Ciena Corporation
IPC分类号： H04B10/40 , H04B10/2507 , H04B10/516 , H04B10/61
CPC分类号： H04B10/40
摘要： A software programmable optical transceiver includes one or more Field Programmable Gate Arrays (FPGAs); and an electro-optical front end communicatively coupled to the one or more FPGAs, wherein the electro-optical front end comprises a transmitter and a receiver, wherein the transmitter is adapted to transmit a transmit signal from the one or more FPGAs and the receiver is adapted to receive a receive signal and provide to the one or more FPGAs, wherein one or more applications are utilized to dynamically configure the one or more FPGAs for digital functionality to operate the software programmable optical transceiver in an associated mode. The one or more applications are loaded as needed to configure the software programmable optical transceiver in the associated mode, without requiring pre-programmed hardware in the software programmable optical transceiver for operation in a plurality of operating modes.
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35.发明申请SYSTEM AND METHOD FOR STATIONARY FINITE IMPULSE RESPONSE FILTERS IN PROGRAMMABLE MICROELECTRONIC CIRCUITS 有权可编程微电子电路中静态有限脉冲响应滤波器的系统与方法公开(公告)号：US20140312931A1
公开(公告)日：2014-10-23
申请号：US13868074
申请日：2013-04-22
申请人： CIENA CORPORATION
IPC分类号： H03K19/003
CPC分类号： H03K19/00346
摘要： A Field Programmable Gate Array (FPGA) to implement channel equalization to mitigate group velocity dispersion in an optical system. In one embodiment, a mapping is loaded into the FPGA whereby the in-phase and quadrature components of the baseband sequence to be filtered are routed to accumulators to form various sums, where each sum is multiplied by a corresponding distinct filter tap coefficient value according to the mapping to form various products, and where the products are summed to provide the in-phase and quadrature components of the filtered output.
摘要翻译： 现场可编程门阵列（FPGA）实现信道均衡以减轻光学系统中的群速度色散。 在一个实施例中，将映射加载到FPGA中，由此将要滤波的基带序列的同相和正交分量路由到累加器以形成各种和，其中每个和乘以相应的不同滤波器抽头系数值，根据 映射以形成各种产品，以及产品相加的位置，以提供过滤输出的同相和正交分量。
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公开(公告)号：US12092860B2
公开(公告)日：2024-09-17
申请号：US18496171
申请日：2023-10-27
申请人： CIENA CORPORATION
发明人： Michael Y. Frankel , John Israel , James Westdorp
IPC分类号： H04B10/08 , G02B6/02 , G02B6/032 , G08B13/186 , H04B10/071 , H04L9/40
CPC分类号： G02B6/02304 , G02B6/02328 , G02B6/032 , G08B13/186 , H04B10/071 , H04L63/162
摘要： A hollow core fiber (HCF) link is characterized by structural properties selected to support and sustain light propagation in a fundamental mode and in at least one higher-order mode. Connected to a proximal end of the HCF link, there is a mode coupler configured to couple a data signal into the fundamental mode and to couple an obfuscating signal into the at least one higher-order mode for simultaneous propagation of the data signal and the obfuscating signal on the HCF link, where the obfuscating signal substantially overlaps the data signal in spectral content. At a distal end of the HCF link, there is a mode splitter configured to split a first optical signal detected in the fundamental mode from a second optical signal detected in the at least one higher-order mode.
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公开(公告)号：US11750531B2
公开(公告)日：2023-09-05
申请号：US16250091
申请日：2019-01-17
申请人： Ciena Corporation
摘要： A data center fabric includes a plurality of Field Programmable Gate Arrays (FPGAs), each FPGA interconnected by a plurality of links with other FPGAs, a plurality of servers in a data center, and physical network functions associated with the data center, wherein the plurality of FPGAs form a virtual fabric for switching between the FPGAs, the plurality of servers, and the physical network functions, and wherein the virtual fabric is arranged in a compound graph and a flat network with each FPGA being a node and a diameter of the compound graph and the flat network is indicative of a maximum number of hops for a packet through the virtual fabric.
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公开(公告)号：US11463176B2
公开(公告)日：2022-10-04
申请号：US17076183
申请日：2020-10-21
申请人： Ciena Corporation
IPC分类号： H04B10/00 , H04B10/572 , H04B10/40 , H04B10/54 , H04B10/548 , H04B10/516
摘要： An electrical circuit package includes an electrical processing engine circuit configured to perform data processing; and one or more co-packaged coherent optical Input/Output (IO) modules interconnected to the electrical processing engine circuit, wherein the electrical processing engine circuit is configured to interface electrical data including an optical signal waveform representation to each of the one or more co-packaged coherent optical IO modules, and wherein the one or more co-packaged coherent optical IO modules are configured to coherently transmit and receive optical data based on the optical signal waveform representation. The electrical processing engine circuit can be configured to perform optical modulation and demodulation based on the optical signal waveform representation, in addition to the data processing.
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公开(公告)号：US20220209868A1
公开(公告)日：2022-06-30
申请号：US17700344
申请日：2022-03-21
申请人： Ciena Corporation
IPC分类号： H04B10/40
摘要： An optical transceiver includes an electro-optic front end; a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC) connected to the electro-optic front end; and one or more Field Programmable Gate Arrays (FPGAs) connected to the DAC and the ADC, wherein the one or more FPGAs are connected to one or more of a local memory and a remote storage for loading FPGA bit files, and wherein the one or more FPGAs are loaded with a forward error correction (FEC) encoding app and a FEC decoding app. The FEC encoding app and the FEC decoding app can be selected based on any of an optical application and a standard compliance requirement.
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公开(公告)号：US20220123841A1
公开(公告)日：2022-04-21
申请号：US17076183
申请日：2020-10-21
申请人： Ciena Corporation
IPC分类号： H04B10/572 , H04B10/40 , H04B10/54
摘要： An electrical circuit package includes an electrical processing engine circuit configured to perform data processing; and one or more co-packaged coherent optical Input/Output (IO) modules interconnected to the electrical processing engine circuit, wherein the electrical processing engine circuit is configured to interface electrical data including an optical signal waveform representation to each of the one or more co-packaged coherent optical IO modules, and wherein the one or more co-packaged coherent optical IO modules are configured to coherently transmit and receive optical data based on the optical signal waveform representation. The electrical processing engine circuit can be configured to perform optical modulation and demodulation based on the optical signal waveform representation, in addition to the data processing.
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