公开(公告)号：US09214526B2

公开(公告)日：2015-12-15

申请号：US14557662

申请日：2014-12-02

Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHA ,  DENSO CORPORATION

Inventor： Hidefumi Takaya ,  Yukihiko Watanabe ,  Sachiko Aoi ,  Atsuya Akiba

IPC: H01L29/78 ,  H01L29/423

CPC classification number: H01L29/4236 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes: a drift layer having a first conductivity type; a body layer having a second conductivity type; a first semiconductor region having the first conductivity type; a gate insulation film; a trench gate electrode; a first main electrode; a second semiconductor region having the second conductivity type; and a conductor region. The first main electrode is electrically connected with the body layer and the first semiconductor region. The second semiconductor region is disposed on a bottom part of the gate trench, and is surrounded by the drift layer. The conductor region is configured to electrically connect the first main electrode with the second semiconductor region and is configured to equalize, when the semiconductor device is in an off-state, a potential of the second semiconductor region and a potential of the first main electrode.

Abstract translation: 半导体器件包括：具有第一导电类型的漂移层; 具有第二导电类型的主体层; 具有第一导电类型的第一半导体区; 栅极绝缘膜; 沟槽栅电极; 第一主电极; 具有第二导电类型的第二半导体区; 和导体区域。 第一主电极与主体层和第一半导体区电连接。 第二半导体区域设置在栅极沟槽的底部，被漂移层包围。 导体区域被配置为将第一主电极与第二半导体区域电连接，并且被配置为当半导体器件处于截止状态时使第二半导体区域的电位和第一主电极的电位相等。

公开(公告)号：US20150236127A1

公开(公告)日：2015-08-20

申请号：US14415752

申请日：2013-08-06

Applicant: Jun MORIMOTO ,  DENSO CORPORATION

Inventor： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Jun Morimoto ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L21/04 ,  H01L21/28 ,  H01L29/04 ,  H01L29/16 ,  H01L21/306

CPC classification number: H01L29/66734 ,  H01L21/049 ,  H01L21/28158 ,  H01L21/30604 ,  H01L29/045 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7813

Abstract: In a method of manufacturing a silicon carbide semiconductor device including a vertical switching element having a trench gate structure, with the use of a substrate having an off angle with respect to a (0001) plane or a (000-1) plane, a trench is formed from a surface of a source region to a depth reaching a drift layer through a base region so that a side wall surface of the trench faces a (11-20) plane or a (1-100) plane, and a gate oxide film is formed without performing sacrificial oxidation after formation of the trench.

Abstract translation: 在制造包括具有沟槽栅极结构的垂直开关元件的碳化硅半导体器件的方法中，通过使用相对于（0001）面或（000-1）面具有偏离角的衬底，使用沟槽 由源极区域的表面形成为通过基底区域到达漂移层的深度，使得沟槽的侧壁表面面向（11-20）面或（1-100）面，并且栅极氧化物 在形成沟槽之后不形成牺牲氧化膜。