公开(公告)号：US08839038B2

公开(公告)日：2014-09-16

申请号：US13372829

申请日：2012-02-14

申请人： Michael John Williams ,  Richard Roy Grisenthwaite

发明人： Michael John Williams ,  Richard Roy Grisenthwaite

IPC分类号： G06F11/00 ,  G06F11/36

CPC分类号： G06F11/2236 ,  G06F11/3632

摘要： A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

摘要翻译： 一种用于控制处理器以单步模式执行使得来自指令流的单个指令被执行的方法和装置，处理器确定单个指令是否是至少一种预定类型的指令中的一种，并将类型指示器存储在 在处理器处理单个指令之后，采集数据存储位置和诊断异常。 此外，执行诊断操作，包括访问存储在数据存储位置中的类型指示符，并且当单个指令不是预定类型中的一个时，控制处理器以单步模式继续执行指令，并且当单个指令 指令是至少一种预定类型之一，控制处理器退出单步模式，并且不执行指令流内的下一条指令作为跟随异常的单个指令。

公开(公告)号：US08417915B2

公开(公告)日：2013-04-09

申请号：US11197523

申请日：2005-08-05

申请人： David Michael Gilday ,  Richard Roy Grisenthwaite

发明人： David Michael Gilday ,  Richard Roy Grisenthwaite

IPC分类号： G06F12/00

CPC分类号： G06F12/1045 ,  G06F12/0864 ,  G06F12/1063

摘要： A virtually indexed and physically tagged memory is described having a cache way size which can exceed the minimum page table size such that aliased virtual addresses VA within the cache way 12 can be mapped to the same physical address PA. Aliasing management logic 10 permits multiple copies of the data from the same physical address to be stored at different virtual indexes within the cache within given or different cache ways.

摘要翻译： 描述了虚拟索引和物理标记的存储器，其具有可以超过最小页表大小的高速缓存路径大小，使得高速缓存路径12内的别名虚拟地址VA可以映射到相同的物理地址PA。 混叠管理逻辑10允许来自相同物理地址的数据的多个副本被存储在给定或不同的高速缓存方式内的高速缓存内的不同虚拟索引处。

公开(公告)号：US08250411B2

公开(公告)日：2012-08-21

申请号：US12318442

申请日：2008-12-30

申请人： Michael John Williams ,  Richard Roy Grisenthwaite ,  Andrew Brookfield Swaine ,  John Michael Horley

发明人： Michael John Williams ,  Richard Roy Grisenthwaite ,  Andrew Brookfield Swaine ,  John Michael Horley

IPC分类号： G06F11/00

CPC分类号： G06F11/3636

摘要： A data processing system 1 has a processor core 2 which is programmable to act as one of a plurality of virtual machines each identified by a virtual machine identifier, each virtual machine acting in one of a plurality of contexts each identified by a context identifier, each context executing a sequence of program instructions, each program instruction having one or more associated memory addresses. The data processing system has diagnostic circuitry 10 for performing diagnostic operations on the processor core. Diagnostic control circuitry 12 is provided which is responsive to current values of the virtual machine identifier, the context identifier and at least one of the one or more associated memory addresses to trigger the diagnostic circuitry 10 to perform diagnostic operations.

摘要翻译： 数据处理系统1具有处理器核心2，其可编程以充当多个虚拟机中的一个，每个虚拟机由虚拟机标识符标识，每个虚拟机以每个由上下文标识符标识的多个上下文之一起作用， 上下文执行程序指令序列，每个程序指令具有一个或多个关联的存储器地址。 数据处理系统具有用于在处理器核上进行诊断操作的诊断电路10。 提供了诊断控制电路12，其响应虚拟机标识符，上下文标识符的当前值和一个或多个相关联的存储器地址中的至少一个来触发诊断电路10执行诊断操作。

公开(公告)号：US20120131312A1

公开(公告)日：2012-05-24

申请号：US13137948

申请日：2011-09-22

申请人： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

发明人： David James Seal ,  Richard Roy Grisenthwaite ,  Nigel John Stephens

IPC分类号： G06F9/30

CPC分类号： G06F9/3016 ,  G06F7/764 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3887

摘要： A data processing apparatus 2 comprises a processing circuit 4 and instruction decoder 6. A bitfield manipulation instruction controls the processing apparatus 2 to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.

摘要翻译： 数据处理装置2包括处理电路4和指令解码器6.位
域操作指令控制处理装置2，从对应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。 比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值 具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。

公开(公告)号：US20120042144A1

公开(公告)日：2012-02-16

申请号：US13067812

申请日：2011-06-28

申请人： Richard Roy Grisenthwaite

发明人： Richard Roy Grisenthwaite

IPC分类号： G06F12/14

CPC分类号： G06F12/145 ,  G06F9/30145 ,  G06F9/30189 ,  G06F2212/1004

摘要： A data processing system 2 including processing circuitry 4 operating in either a first mode or a second mode. Page table data 30 including access control bits 40, 42, is used to control permissions for memory access to memory pages. In the first mode, the access control bits include at least one instance of a redundant encoding. In the second mode, the redundant encoding is removed to provide more efficient use of the access control bit encoding space.

摘要翻译： 数据处理系统2包括以第一模式或第二模式操作的处理电路4。 包括访问控制位40,42的页表数据30用于控制对存储器页的存储器访问的许可。 在第一模式中，访问控制位包括冗余编码的至少一个实例。 在第二模式中，去除冗余编码以提供更有效地使用访问控制位编码空间。

公开(公告)号：US20110087819A1

公开(公告)日：2011-04-14

申请号：US12923727

申请日：2010-10-05

申请人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

发明人： Peter Andrew Riocreux ,  Bruce James Mathewson ,  Christopher William Laycock ,  Richard Roy Grisenthwaite

IPC分类号： G06F13/14

CPC分类号： G06F13/362 ,  G06F13/1621 ,  G06F13/1689 ,  G06F13/364

摘要： Interconnect circuitry for a data processing apparatus is disclosed. The interconnect circuitry is configured to provide data routes via which at least one initiator device may access at least one recipient device, said interconnect circuitry comprising: at least one input for receiving transaction requests from said at least one initiator device; at least one output for outputting transaction requests to said at least one recipient device; at least one path for transmitting said transaction requests between said at least one input and said at least one output; control circuitry for routing said received transaction requests from said at least one input to said at least one output; wherein said control circuitry is configured to respond to a barrier transaction request to maintain an ordering of at least some transaction requests with respect to said barrier transaction request within a stream of transaction requests passing along one of said at least one paths, by not allowing reordering of at least some transactions requests that occur before said barrier transaction request in said stream of transaction requests with respect to at least some transaction requests that occur after said bather transaction request in said stream of transaction requests; wherein said bather transaction request comprising an indicator indicating which of said transaction requests within said stream of transaction requests comprise said at least some transaction requests whose ordering is to be maintained.

摘要翻译： 公开了一种用于数据处理装置的互连电路。 所述互连电路被配置为提供数据路由，至少一个发起者设备可经由该路径访问至少一个接收方设备，所述互连电路包括：用于从所述至少一个启动器设备接收事务请求的至少一个输入; 用于向所述至少一个接收设备输出交易请求的至少一个输出; 用于在所述至少一个输入和所述至少一个输出之间传送所述事务请求的至少一个路径; 用于将所述接收的交易请求从所述至少一个输入路由到所述至少一个输出的控制电路; 其中所述控制电路被配置为响应于屏障事务请求，以通过不允许重新排序来保持在通过所述至少一个路径之一的事务请求流内关于所述屏障事务请求的至少一些事务请求的排序 在所述事务请求流中的所述屏障事务请求之前发生的至少一些事务请求相对于在所述事务请求流中的所述沐浴事务请求之后发生的至少一些事务请求; 其中所述沐浴事务请求包括指示所述事务请求流内的所述事务请求中的哪一个包括所述至少一些其顺序要保持的事务请求的指示符。

公开(公告)号：US07805550B2

公开(公告)日：2010-09-28

申请号：US11032226

申请日：2005-01-11

申请人： Paul Kimelman ,  Richard Roy Grisenthwaite

发明人： Paul Kimelman ,  Richard Roy Grisenthwaite

IPC分类号： G06F3/00 ,  G06F15/16 ,  G06F15/00

CPC分类号： G06F13/24 ,  G06F1/3228

摘要： A data processing apparatus and method are provided for managing polling loops. The data processing apparatus comprises a main processing unit and a subsidiary processing unit operable to perform a task on behalf of the main processing unit. The subsidiary processing unit is operable to set a completion field when the task has been completed and the main processing unit is operable to poll the completion field in order to determine whether the task has been completed. If on polling the completion field a threshold number of times the main processing unit determines that the task has not been completed, the main processing unit is operable to enter a power saving mode. The subsidiary processing unit is operable, when the task has been completed, to cause a notification to be issued on a path interconnecting the main processing unit and the subsidiary processing unit. The main processing unit is arranged, upon receipt of the notification to exit the power saving mode. This provides a particularly efficient technique for managing a polling loop within the data processing apparatus.

摘要翻译： 提供了一种用于管理轮询循环的数据处理装置和方法。 数据处理装置包括主处理单元和辅助处理单元，可操作以代表主处理单元执行任务。 辅助处理单元可操作以在任务完成时设置完成字段，并且主处理单元可操作地轮询完成字段以便确定任务是否已经完成。 如果在轮询完成字段时，主处理单元确定任务尚未完成的阈值次数，则主处理单元可操作以进入省电模式。 当完成任务时，辅助处理单元可操作地在连接主处理单元和辅助处理单元的路径上发出通知。 主处理单元在接收到退出省电模式的通知时被布置。 这提供了一种用于管理数据处理装置内的轮询循环的特别有效的技术。

公开(公告)号：US07797520B2

公开(公告)日：2010-09-14

申请号：US11170083

申请日：2005-06-30

申请人： Gilles Eric Grandou ,  Phillippe Jean-Pierre Raphalen ,  Richard Roy Grisenthwaite

发明人： Gilles Eric Grandou ,  Phillippe Jean-Pierre Raphalen ,  Richard Roy Grisenthwaite

IPC分类号： G06F9/00

CPC分类号： G06F9/3844 ,  G06F9/3804

摘要： A data processing apparatus including a prefetch unit for prefetching the instructions from a memory, branch prediction logic and a branch target cache for storing predetermined information about branch operations executed by the processor. The information includes identification of an instruction specifying a branch operation, a target address for said branch operation and a prediction as to whether said branch operation is taken or not. The prefetch unit accesses said branch target cache at least one clock cycle prior to fetching an instruction from said memory, to determine if there is predetermined information corresponding to said instruction stored within said branch target cache.

摘要翻译： 一种数据处理装置，包括用于从存储器预取指令的预取单元，分支预测逻辑和用于存储关于由处理器执行的分支操作的预定信息的分支目标高速缓存。 该信息包括指定分支操作的指令的标识，用于所述分支操作的目标地址以及是否采用所述分支操作的预测。 预取单元在从所述存储器取出指令之前至少一个时钟周期访问所述分支目标高速缓存，以确定是否存在与存储在所述分支目标高速缓存中的所述指令相对应的预定信息。

公开(公告)号：US07757027B2

公开(公告)日：2010-07-13

申请号：US12213470

申请日：2008-06-19

申请人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

发明人： Christopher William Laycock ,  Antony John Harris ,  Bruce James Mathewson ,  Richard Roy Grisenthwaite ,  Stuart David Biles

IPC分类号： G06F13/00

CPC分类号： G06F13/4221

摘要： An integrated circuit 2 includes a transaction master 4 connected via interconnect circuitry 10 to a transaction slave 12. The transaction slave 12 generates a transfer-complete signal (R Last or B) to indicate completion of a data transfer (either a read or a write). When this transfer-complete signal has been received by the transaction master 4, then the transaction master 4 generates a complete-acknowledgement signal RACK, WACK, which is passed back to the transaction slave so as to acknowledge receipt of the transfer-complete signal.

摘要翻译： 集成电路2包括经由互连电路10连接到交易从属单元12的交易主机4.交易从机12产生传输完成信号（R Last或B）以指示完成数据传送（读或写 ）。 当该传输完成信号已被交易主机4接收到时，交易主机4产生一个完整确认信号RACK，其返回到交易从属单元，以便确认传送完成信号的接收。

公开(公告)号：US20090125756A1

公开(公告)日：2009-05-14

申请号：US11984221

申请日：2007-11-14

申请人： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite ,  Michael John Williams

发明人： Andrew Brookfield Swaine ,  Richard Roy Grisenthwaite ,  Michael John Williams

IPC分类号： G06F11/34

CPC分类号： G06F11/3476 ,  G06F11/348 ,  G06F2201/865

摘要： A data processing apparatus is provided, comprising monitored circuitry for performing activities, trace circuitry for producing a stream of trace elements representative of at least some of these activities, and detection circuitry for detecting the occurrence of a predetermined subset of the activities for which the trace circuitry is producing trace elements. When an activity in that predetermined subset of activities is detected a timing indication is added to the stream of trace elements. Hence, the valuable trace bandwidth- may be preserved, by limiting the trace elements for which a timing indication is added into the trace stream to a predetermined subset of the activities for which trace elements are generated, and the valuable global or relative timing accuracy of those activities represented in the trace stream is retained, without flooding the trace stream with timing indications.

摘要翻译： 提供了一种数据处理装置，包括用于执行活动的被监测电路，用于产生表示这些活动中的至少一些的微量元素流的跟踪电路，以及检测电路，用于检测所述活动的预定子集的发生 电路正在产生微量元素。 当检测到该预定活动子集中的活动时，将定时指示添加到微量元素流。 因此，可以通过将跟踪流中添加定时指示的跟踪元素限制到生成微量元素的活动的预定子集，并将有价值的全局或相对定时精度保留在有价值的跟踪带宽中 在跟踪流中表示的那些活动被保留，而不会使跟踪流与时间指示淹没。