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公开(公告)号：US20050118973A1
公开(公告)日：2005-06-02
申请号：US10481977
申请日：2002-06-03
申请人： Nadim Khlat
发明人： Nadim Khlat
CPC分类号： H03D7/165 , H03J5/0272 , H03J7/065 , H03L7/1974 , H04B1/30
摘要： Local oscillator apparatus comprising communication signal terminals (LNA IN, LNA INX; RF OUT,RF OUTN) for a communication signal, especially in a receiver or a transmitter, and a controlled frequency oscillator (204; 404) for producing a local oscillator signal. The local oscillator also includes a reference frequency generator (210; 410) and a feedback loop (208;408) for selecting and adjusting the frequency (fVCO) of the local oscillator signal relative to the frequency (fxtal) of said reference frequency signal. A first frequency divider (205; 405) divides the frequency of the local oscillatr signal by a first division factor (M) to produce a conversion signal, where the frequency (FILO) of said conversion signal is at least approximately equal to the frequency (fRF) of the communication signal, and conversion means (202,203; 402, 403) responsive to the conversion signal converts between said communication signal and a base-band signal. A second frequency divider (206;406) divides the frequency of the local oscillator signal by a second division factor (N) and is connected in the feedback loop, where the first division factor (N) is different to the second division factor (M) and the ratios between said first and second division factors (M/N, N/M) are fractional.
摘要翻译： 本地振荡器装置包括用于通信信号的通信信号端（LNA IN，LNA INX; RF OUT，RF OUTN），特别是在接收机或发射机中，以及用于产生本地振荡器信号的受控频率振荡器（204,404）。 本地振荡器还包括参考频率发生器（210; 410）和用于相对于所述参考频率信号的频率（fxtal）选择和调整本地振荡器信号的频率（fVCO）的反馈回路（208; 408）。 第一分频器（205; 405）将本地振荡器信号的频率除以第一分频因子（M）以产生转换信号，其中所述转换信号的频率（FILO）至少近似等于频率 fRF）和响应于转换信号的转换装置（202,203; 402,403）在所述通信信号和基带信号之间进行转换。 第二分频器（206; 406）将本地振荡器信号的频率除以第二分频因子（N），并连接在反馈环路中，其中第一分频因子（N）不同于第二分频因子（M ），并且所述第一和第二分割因子（M / N，N / M）之间的比率是分数的。
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公开(公告)号：US06678340B1
公开(公告)日：2004-01-13
申请号：US09535396
申请日：2000-03-24
申请人： Nadim Khlat , Patrick Clement
发明人： Nadim Khlat , Patrick Clement
IPC分类号： H04B110
摘要： Apparatus 20,30,40,50 for receiving and processing a wanted Radio Frequency signal comprises a radio frequency to intermediate frequency down-conversion stage 20 for receiving the wanted radio frequency signal and out-putting a complex intermediate frequency signal; an analogue to digital converter 30 for converting the complex intermediate frequency signal to a digital complex intermediate signal; an intermediate frequency to base-band down-conversion stage 40 for receiving the digital complex intermediate frequency signal and out-putting a digital complex base-band signal; and a complex notch filter 50 for receiving the digital complex base-band signal and out-putting a notch filtered digital complex base-band signal wherein the complex notch filter 50 substantially filters out a small portion of the base-band signal centred about a first, non-zero, frequency while substantially passing a corresponding portion of the base-band signal centred about a second frequency having the same magnitude but opposite sign to the first frequency.
摘要翻译： 用于接收和处理所需射频信号的设备20,30,40,50包括用于接收所需射频信号并输出复合中频信号的射频至中频下变频级20; 用于将复合中频信号转换为数字复合中间信号的模数转换器30; 中频到基带下变频级40，用于接收数字复合中频信号并输出数字复基带信号; 以及用于接收数字复基带信号并输出陷波滤波的数字复基带信号的复陷波滤波器50，其中复陷波滤波器50基本上过滤掉以第一和第二信号为中心的基带信号的一小部分 ，非零频率，同时基本上将以具有相同幅度但相反符号的第二频率为中心的基带信号的对应部分传送到第一频率。
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公开(公告)号：US09954436B2
公开(公告)日：2018-04-24
申请号：US13876518
申请日：2011-09-29
申请人： Nadim Khlat
发明人： Nadim Khlat
CPC分类号： H02M3/07 , H02M2001/009 , Y10T307/406
摘要： The detailed description described embodiments of highly efficient power management systems configurable to simultaneously generate various output voltage levels for different components, sub-assemblies, and devices of electronic devices, sub-systems, and systems. In particular, the described embodiments include power management systems that substantially reduce or eliminate the need for inductors, large numbers of capacitors, and complex switching techniques to transform an available voltage level from a system power source, such as a battery, to more desirable power supply voltages. Some described embodiments include a charge pump that uses only two flying capacitors to simultaneously generate multiple supply outputs, where each of the multiple supply outputs may provide either the same or a different output voltage level. The described embodiments also include efficient power management systems that flexibly provide highly accurate voltage levels that are substantially insensitive to the voltage level provided by a system power source, such as a battery.
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公开(公告)号：US09263996B2
公开(公告)日：2016-02-16
申请号：US13552768
申请日：2012-07-19
CPC分类号： H03F3/189 , H03F1/0222 , H03F2200/411
摘要： A method of defining a quasi iso-gain supply voltage function for an envelope tracking system is disclosed. The method includes a step of capturing iso-gain supply voltage values versus power values for a device under test (DUT). Other steps involve locating a minimum iso-gain supply voltage value, and then replacing the iso-gain supply voltage values with the minimum iso-gain supply voltage value for corresponding output power values that are less than an output power value corresponding to the minimum iso-gain supply voltage value. The method further includes a step of generating a look-up table (LUT) of iso-gain supply voltage values as a function of input power for the DUT after the step of replacing the iso-gain supply voltage values with the minimum iso-gain supply voltage value for corresponding output power values that are less than an output power value corresponding to the minimum iso-gain supply voltage value.
摘要翻译： 公开了一种定义用于包络跟踪系统的准等增益电源电压功能的方法。 该方法包括捕获等效增益电源电压值与被测器件（DUT）的功率值的步骤。 其他步骤包括定位最小等电位增益电源电压值，然后用对应于最小等效电流的输出功率值的相应输出功率值的最小等效增益电源电压值替换等增益电源电压值 - 电源电压值。 该方法还包括以下步骤：在以等于最小等效增益替换等增益电源电压值的步骤之后，产生作为DUT的输入功率的函数的等增益电源电压值的查找表（LUT） 对于相应的输出功率值的电源电压值小于对应于最小等
差增益电源电压值的输出功率值。-
公开(公告)号：US09112570B2
公开(公告)日：2015-08-18
申请号：US13020548
申请日：2011-02-03
申请人： Nadim Khlat , Marcus Granger-Jones
发明人： Nadim Khlat , Marcus Granger-Jones
CPC分类号： H04B1/1036
摘要： A tunable receiver system uses programmable notch filters to identify available channel pairs for transmitting and receiving data via a femtocell base station. In addition, one of the programmable notch filters may be used to suppress infiltration of the transmit path signal into the receiver path of the receiver device. The other programmable notch filter may be used to suppress a blocker signal identified by the receiver device.
摘要翻译： 可调谐接收机系统使用可编程陷波滤波器来识别用于经由毫微微小区基站发送和接收数据的可用信道对。 此外，可编程陷波滤波器之一可以用于抑制发射路径信号进入接收机设备的接收机路径的渗透。 另一个可编程陷波滤波器可用于抑制由接收机设备识别的阻塞信号。
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公开(公告)号：US09075673B2
公开(公告)日：2015-07-07
申请号：US13297470
申请日：2011-11-16
申请人： Nadim Khlat , Shanthi Prasad
发明人： Nadim Khlat , Shanthi Prasad
CPC分类号： G06F7/556 , G06F1/0307 , H03F1/0227 , H03M7/04
摘要： A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.
摘要翻译： 公开了对数字线性增益乘数的数字对数增益。 对数字线性增益乘数的数字对数增益包括一个对数增益分配器，适用于将日志增益输入分解为整数对数部分和余数对数部分。 对数缩放比例转换器适于响应于整数对数部分和其余日志部分输出线性增益值。 增益乘法电路适于将数字信号乘以线性增益值以输出增益增强数字信号。
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公开(公告)号：US08942313B2
公开(公告)日：2015-01-27
申请号：US13367973
申请日：2012-02-07
CPC分类号： H03F1/0227 , H03F3/24 , H03F2200/411 , H03F2200/447 , H03F2200/465
摘要： An open loop envelope tracking system calibration technique and circuitry are proposed. A radio frequency power amplifier receives a modulated signal. An envelope tracker power converter generates a modulated power amplifier supply voltage for the radio frequency power amplifier based on a control signal derived from the modulated signal. A first output power and a second output power of the radio frequency power amplifier are measured when the control signal is respectively delayed by a first delay period and a second delay period. A sensitivity of the output power of the radio frequency power amplifier is near a maximum near the first delay period and the second delay period. The first delay period and/or the second delay period are adjusted until the first output power substantially equals the second output power. The first delay period and the second delay period are used to obtain a calibrated fine tuning delay offset.
摘要翻译： 提出了开环包络跟踪系统校准技术和电路。 射频功率放大器接收调制信号。 信封跟踪器功率转换器基于从调制信号导出的控制信号，为射频功率放大器生成调制功率放大器电源电压。 当控制信号分别延迟第一延迟周期和第二延迟周期时，测量射频功率放大器的第一输出功率和第二输出功率。 射频功率放大器的输出功率的灵敏度在第一延迟周期和第二延迟周期附近接近最大值。 第一延迟周期和/或第二延迟周期被调整直到第一输出功率基本上等于第二输出功率。 第一延迟周期和第二延迟周期用于获得经校准的微调延迟偏移。
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公开(公告)号：US08682260B1
公开(公告)日：2014-03-25
申请号：US12607634
申请日：2009-10-28
CPC分类号： H04B1/0475 , H04B1/0067
摘要： The present disclosure relates to a multi-band RF power amplifier (PA) module, which is used to receive, filter, and amplify a first RF input signal to provide a first RF output signal using a first tunable bandpass and notch filter. The multi-band RF PA module may include a supporting substrate having at least a first inductive element that provides a first portion of the first tunable bandpass and notch filter. Further, the multi-band RF PA module may include at least a first semiconductor die, which is attached to the supporting substrate and provides a second portion of the first tunable bandpass and notch filter. A transceiver module may provide the first RF input signal.
摘要翻译： 本公开涉及一种多频带RF功率放大器（PA）模块，其用于接收，滤波和放大第一RF输入信号，以使用第一可调谐带通和陷波滤波器提供第一RF输出信号。 多频带RF PA模块可以包括具有至少第一感应元件的支撑衬底，其提供第一可调谐带通和陷波滤波器的第一部分。 此外，多频带RF PA模块可以包括至少第一半导体管芯，其连接到支撑衬底并提供第一可调谐带通和陷波滤波器的第二部分。 收发器模块可以提供第一RF输入信号。
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39.发明授权Split-band power amplifiers and duplexers for LTE-advanced front end for improved IMD 有权用于LTE高级前端的分频功率放大器和双工器，用于改进IMD公开(公告)号：US08644198B2
公开(公告)日：2014-02-04
申请号：US13045621
申请日：2011-03-11
IPC分类号： H04B7/00
CPC分类号： H03F3/24 , H03F3/189 , H03F3/211 , H03F3/68 , H03F2200/222 , H03F2200/249 , H03F2200/318 , H03F2200/387 , H03F2200/411 , H03F2200/451 , H03F2200/534 , H03F2200/537 , H03F2200/541 , H03F2200/81
摘要： A front end radio architecture (FERA) is disclosed that includes a transmitter block coupled to a power amplifier (PA) via first and second input terminals. A first split-band duplexer is coupled to a first output terminal of the PA and a second split-band duplexer is coupled to a second output terminal of the PA. The PA includes a first amplifier cell and a second amplifier cell that when coupled to the first and second split-band duplexers makes up first and second transmitter chains. Only one of the first and the second transmitter chains is active when a first carrier and a second carrier have a frequency offset that is less than an associated half duplex frequency within a same split-band duplex band, thus preventing third order inter-modulation (IMD) products from falling within an associated receive channel. Otherwise, the first and the second transmitter chains are both active.
摘要翻译： 公开了一种前端无线电架构（FERA），其包括经由第一和第二输入端子耦合到功率放大器（PA）的发射机模块。 第一分波分双工器耦合到PA的第一输出端，而第二分波分双工器耦合到PA的第二输出端。 PA包括第一放大器单元和第二放大器单元，当耦合到第一和第二分离带双工器组成第一和第二发送器链时。 当第一载波和第二载波具有小于相同分离带双工频带内的相关联的半双工频率的频率偏移时，第一和第二发射机链中只有一个有效，从而防止三阶互调（ IMD）产品落入相关接收渠道内。 否则，第一和第二发射机链都是活动的。
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40.发明授权Extracting clock information from a serial communications bus for use in RF communications circuitry 有权从串行通信总线提取时钟信息，用于RF通信电路公开(公告)号：US08521101B1
公开(公告)日：2013-08-27
申请号：US12884933
申请日：2010-09-17
IPC分类号： H04B1/38
CPC分类号： H04L7/04 , G06F13/385 , H04J3/0685
摘要： The present disclosure relates to RF front-end (RFFE) circuitry that includes multiple RFFE circuits, each of which may be provided by a separate integrated circuit (IC), front-end module, or both. As such, the RFFE circuits may be connected to one another using an RFFE serial communications bus. Further, one or more of the RFFE circuits may need an accurate clock source for analog-to-digital conversion (ADC), digital-to-analog conversion (DAC), calibration, sensor measurements, or the like. Instead of including an integral clock source circuit or receiving a separate external clock signal, an RFFE circuit may extract clock information from the RFFE serial communications bus to provide one or more clock signal. The clock information may be associated with one or more serial communications command via the RFFE serial communications bus, may be associated with alternate functionality of the RFFE serial communications bus, or both.
摘要翻译： 本公开涉及包括多个RFFE电路的RF前端（RFFE）电路，每个RFFE电路可以由单独的集成电路（IC），前端模块或两者提供。 因此，RFFE电路可以使用RFFE串行通信总线彼此连接。 此外，一个或多个RFFE电路可能需要用于模数转换（ADC），数模转换（DAC），校准，传感器测量等的精确时钟源。 RFFE电路不是包括集成时钟源电路或者接收单独的外部时钟信号，而是可以从RFFE串行通信总线提取时钟信息以提供一个或多个时钟信号。 时钟信息可以经由RFFE串行通信总线与一个或多个串行通信命令相关联，可以与RFFE串行通信总线或两者的备用功能相关联。
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