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1.发明授权Method of operating radio receiver implemented in a single CMOS integrated circuit 有权在单个CMOS集成电路中实现无线电接收机的操作方法公开(公告)号：US08095105B2
公开(公告)日：2012-01-10
申请号：US11871100
申请日：2007-10-11
IPC分类号： H04B1/28
CPC分类号： H04B1/1027 , H03J5/0272 , H03L7/197 , H04B1/26 , H04B1/28
摘要： A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
摘要翻译： 本文公开了一种单芯片超高音AM接收机。 为了补偿IC的实现中的工艺变化，基于本地振荡器中的PLL电路中的频率控制信号来调整设定系统中各种放大器和其它部件的工作条件的偏置电流。 由于控制信号的幅度反映了过程变化，所以基于控制信号调整偏置电流以抵消接收器其它部分中的这些变化。 为了进一步提高接收机的信噪比，将IF滤波器调谐到一定范围内，以便不包括定时参考频率的任何整数倍或整数除数。 描述了各种技术，用于使得能够在接收天线输入信号并输出数字数据信号的单个芯片上实现完整的超临界AM接收机。
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2.发明授权公开(公告)号：US07962117B2
公开(公告)日：2011-06-14
申请号：US11610478
申请日：2006-12-13
IPC分类号： H04B1/28
CPC分类号： H04B1/1027 , H03J5/0272 , H03L7/197 , H04B1/26 , H04B1/28
摘要： A single chip receiver is disclosed herein. The chip only requires an external antenna for operation. A decoder is formed on chip for performing logical operations on demodulated digital data. A baseband filter is controlled by external control signals to have one of a plurality of discrete frequency response bandwidths depending on the type of signal to be received. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
摘要翻译： 本文公开了一种单芯片接收机。 该芯片只需要外部天线进行操作。 解码器形成在芯片上，用于对解调的数字数据进行逻辑运算。 基带滤波器由外部控制信号控制，以根据要接收的信号的类型具有多个离散频率响应带宽中的一个。 为了补偿IC的实现中的工艺变化，基于本地振荡器中的PLL电路中的频率控制信号来调整设定系统中各种放大器和其它部件的工作条件的偏置电流。 由于控制信号的幅度反映了过程变化，所以基于控制信号调整偏置电流以抵消接收器其它部分中的这些变化。 为了进一步提高接收机的信噪比，将IF滤波器调谐到一定范围内，以便不包括定时参考频率的任何整数倍或整数除数。 描述了各种技术，用于使得能够在接收天线输入信号并输出数字数据信号的单个芯片上实现完整的接收机。
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3.发明授权Method of operating radio receiver implemented in a single CMOS integrated circuit 有权在单个CMOS集成电路中实现无线电接收机的操作方法公开(公告)号：US07299029B2
公开(公告)日：2007-11-20
申请号：US10661879
申请日：2003-09-11
IPC分类号： H04B1/28
CPC分类号： H04B1/1027 , H03J5/0272 , H03L7/197 , H04B1/26 , H04B1/28
摘要： A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
摘要翻译： 本文公开了一种单芯片超高音AM接收机。 为了补偿IC的实现中的工艺变化，基于本地振荡器中的PLL电路中的频率控制信号来调整设定系统中各种放大器和其它部件的工作条件的偏置电流。 由于控制信号的幅度反映了过程变化，所以基于控制信号调整偏置电流以抵消接收器其它部分中的这些变化。 为了进一步提高接收机的信噪比，将IF滤波器调谐到一定范围内，以便不包括定时参考频率的任何整数倍或整数除数。 描述了各种技术，用于使得能够在接收天线输入信号并输出数字数据信号的单个芯片上实现完整的超临界AM接收机。
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公开(公告)号：US07038496B2
公开(公告)日：2006-05-02
申请号：US09995470
申请日：2001-11-28
申请人： David Canard , Vincent Fillatre
发明人： David Canard , Vincent Fillatre
IPC分类号： G01R23/02
CPC分类号： H03J5/0272 , H03D13/003 , H03L7/085 , H03L7/0891
摘要： The present invention relates to a device for comparison CMP, which is designed to emit a control signal Vcnt, which is representative of a difference which exists between the input signal frequencies Vdiv and Vref. The device according to the invention includes a phase/frequency comparator PD, which supplies a regulation signal Tun, which is subjected to pulse width modulation according to the difference observed. The device also includes a current source, which is designed to emit a charge current Ics, with a value which is controlled by the regulation signal Tun. The device further includes a capacitive element Cs, which is designed to generate the control signal Vcnt, under the effect of the charge current Ics. By means of a regulation signal Tun, which has a frequency which is virtually constant, the invention makes it possible to impose high-frequency variations on the control signal Vcnt.
摘要翻译： 本发明涉及用于比较CMP的器件，其被设计为发射表示存在于输入信号频率Vdiv和Vref之间的差的控制信号Vcnt。 根据本发明的装置包括相位/频率比较器PD，该相位/频率比较器PD提供调节信号Tun，该调节信号Tun根据观测到的差异进行脉冲宽度调制。 该装置还包括电流源，其被设计为发射具有由调节信号Tun控制的值的充电电流Ics。 该装置还包括在充电电流Ics的作用下设计成产生控制信号Vcnt的电容元件Cs。 通过具有几乎恒定的频率的调节信号Tun，本发明使得可以对控制信号Vcnt施加高频变化。
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5.发明授权Component having an acoustically active material for tuning during operation 有权具有用于在操作期间调谐的声学活性材料的部件公开(公告)号：US06847271B2
公开(公告)日：2005-01-25
申请号：US10381364
申请日：2001-09-20
申请人： Christian Korden , Thomas Ostertag , Werner Ruile
发明人： Christian Korden , Thomas Ostertag , Werner Ruile
CPC分类号： H03L7/18 , H03H3/04 , H03H9/6403 , H03H2009/02196 , H03J3/08 , H03J3/28 , H03J5/0272 , H03L7/0805
摘要： A component having an acoustically active material, whose acoustic constants can be at least partially altered. The acoustically active material is located at least partially at a phase transition point and/or in the vicinity of a phase transition point.
摘要翻译： 具有声学活性材料的组分，其声学常数可以至少部分地改变。 声学活性材料至少部分地位于相变点和/或相转变点附近。
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公开(公告)号：US20040058663A1
公开(公告)日：2004-03-25
申请号：US10661879
申请日：2003-09-11
申请人： Micrel Incorporated
IPC分类号： H04B001/06 , H04B001/26
CPC分类号： H04B1/1027 , H03J5/0272 , H03L7/197 , H04B1/26 , H04B1/28
摘要： A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
摘要翻译： 本文公开了一种单芯片超高音AM接收机。 为了补偿IC的实现中的工艺变化，基于本地振荡器中的PLL电路中的频率控制信号来调整设定系统中各种放大器和其它部件的工作条件的偏置电流。 由于控制信号的幅度反映了过程变化，所以基于控制信号调整偏置电流以抵消接收器其它部分中的这些变化。 为了进一步提高接收机的信噪比，将IF滤波器调谐到一定范围内，以便不包括定时参考频率的任何整数倍或整数除数。 描述了各种技术，用于使得能够在接收天线输入信号并输出数字数据信号的单个芯片上实现完整的超临界AM接收机。
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公开(公告)号：US06662003B2
公开(公告)日：2003-12-09
申请号：US09734844
申请日：2000-12-11
IPC分类号： H04B128
CPC分类号： H04B1/1027 , H03J5/0272 , H03L7/197 , H04B1/26 , H04B1/28
摘要： A single chip superhetrodyne AM receiver is disclosed herein. To compensate for process variations in the implementation of the IC, bias currents setting the operating conditions for various amplifiers and other components in the system are adjusted based on frequency control signals in a PLL circuit in the local oscillator. Since the magnitude of the control signal reflects the process variations, the bias currents are adjusted based on the control signal to offset these variations in other portions of the receiver. To further improve the signal to noise ratio of the receiver, the IF filter is tuned within a range so as not to include any integer multiple or integer divisor of the timing reference frequency. Various techniques are described for enabling a complete superhetrodyne AM receiver to be implemented on a single chip which receives an antenna input signal and outputs a digital data signal.
摘要翻译： 本文公开了一种单芯片超高音AM接收机。 为了补偿IC的实现中的工艺变化，基于本地振荡器中的PLL电路中的频率控制信号来调整设定系统中各种放大器和其它部件的工作条件的偏置电流。 由于控制信号的幅度反映了过程变化，所以基于控制信号调整偏置电流以抵消接收器其它部分中的这些变化。 为了进一步提高接收机的信噪比，将IF滤波器调谐到一定范围内，以便不包括定时参考频率的任何整数倍或整数除数。 描述了各种技术，用于使得能够在接收天线输入信号并输出数字数据信号的单个芯片上实现完整的超临界AM接收机。
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公开(公告)号：US6163182A
公开(公告)日：2000-12-19
申请号：US060089
申请日：1998-04-14
申请人： David Canard , Vincent Fillatre
发明人： David Canard , Vincent Fillatre
CPC分类号： H03J5/0272 , H03K23/542
摘要： A frequency divider DIV/4 composed of memory cells (DL1 . . . DL4) realized in ECL technology, whose data paths constitute a loop, the data output Q4 of the last memory cell DL4 being cross-connected to the data input D1 of the first memory cell DL1. The clock inputs Ck of the memory cells DL1, DL3 of the odd rank are connected to the input IN of the frequency divider circuit DIV/4, while the others are cross-connected to said input. Such a frequency divider generates a noise having a unique frequency which is twice the frequency of the input signal, irrespective of the division ratio obtained.
摘要翻译： 由ECL技术实现的存储单元（DL1 ... DL4）组成的分频器DIV / 4，其数据路径构成一个环路，最后一个存储单元DL4的数据输出端Q4交叉连接到数据输入端 第一存储单元DL1。 奇数级的存储单元DL1，DL3的时钟输入Ck连接到分频器电路DIV / 4的输入IN，而其它的与交叉连接到所述输入。 这种分频器产生具有独特频率的噪声，该频率是输入信号频率的两倍，而与获得的分频比无关。
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9.发明授权Apparatus and method of setting variable dividing ratio and apparatus using the same 失效设置可变分频比的装置和方法及使用其的装置
公开(公告)号：US5712595A
公开(公告)日：1998-01-27
申请号：US611900
申请日：1996-03-06
申请人： Hiroshi Yokoyama
发明人： Hiroshi Yokoyama
CPC分类号： H03J5/0272 , G06F7/68 , H03K23/667 , H03L7/183 , H03L7/193
摘要： A counter apparatus for setting a dividing ratio given as a sum of a fixed value and a variable value, including an upper-digits-setting circuit for setting upper digits of a series of digits representing the dividing ratio to upper predetermined digits, the upper digits being fixed digits composing upper digits of a series of digits representing the fixed value; an adder for adding fixed digits composing middle digits of the series of digits representing the fixed value and variable digits composing upper digits of a series of digits representing the variable value and providing an output thereof as middle digits of the series of digits representing the dividing ratio which are variable digits; a middle-digits-setting circuit for setting the middle digits of the series of digits representing the dividing ratio to middle predetermined digits; and a lower-digits-setting circuit for setting lower digits of the series of digits representing the dividing ratio to lower predetermined digits, the lower digits being variable digits composing lower digits of the series of digits representing the variable value.
摘要翻译： 用于设定给定为固定值和可变值之和的分频比的计数器装置，包括用于将表示分割比的一系列数字的高位数字设置为高位预定数字的高位数字设置电路，高位数字 是组成表示固定值的一系列数字的高位数字的固定数字; 一个加法器，用于添加构成表示固定值的一系列数字的中间位数的固定数字和构成表示可变值的一系列数字的高位数字的可变数字，并将其输出作为表示分频比的一系列数字的中间位数 它们是可变数字; 中间位设置电路，用于将表示分割比的一系列数字的中间位数设置为中间预定数字; 以及低位数设置电路，用于将表示分频比的一系列数字的低位数字设置为较低的预定数字，低位数字是构成表示可变值的一系列数字的低位数字的可变数字。
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10.发明授权Digital radio system capable of high-speed frequency changing at low power consumption 失效数字无线电系统能够以低功耗高速频率变化
公开(公告)号：US5603097A
公开(公告)日：1997-02-11
申请号：US517196
申请日：1995-08-21
申请人： Hideto Kanou
发明人： Hideto Kanou
CPC分类号： H03D7/161 , H03J5/0272 , H03L7/185
摘要： The output frequency of a PLL frequency synthesizer and the output frequency of a fixed oscillator are mixed together in a mixer to produce sum and difference frequencies. The sum frequency is used as a local frequency, and the difference frequency is fed back to the PLL frequency synthesizer. In addition, the output frequency of the fixed oscillator is divided in a predetermined ratio to use it as a local frequency for the second or other subsequent frequency converting stage on the receiver or transmitter side.
摘要翻译： PLL频率合成器的输出频率和固定振荡器的输出频率在混频器中混合在一起以产生和频和差分频率。 和频率用作本地频率，差频被反馈给PLL频率合成器。 此外，固定振荡器的输出频率以预定比例被分频，以将其用作接收机或发射机侧的第二或其它后续频率转换级的本地频率。
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