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    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS
    32.
    发明申请
    METHOD AND SYSTEM FOR EVALUATING STATISTICAL SENSITIVITY CREDIT IN PATH-BASED HYBRID MULTI-CORNER STATIC TIMING ANALYSIS 失效
    基于路径的混合多角度静态时序分析评估统计灵敏度信息的方法和系统

    公开(公告)号：US20080209373A1

    公开(公告)日：2008-08-28

    申请号：US11679251

    申请日：2007-02-27

    申请人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    发明人： Nathan C. Buck ,  John P. Dubuque ,  Eric A. Foreman ,  Peter A. Habitz ,  Kerim Kalafala ,  Peihua Qi ,  Chandramouli Visweswariah ,  Xiaoyue Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Methods, systems and computer program products for analyzing a timing design of an integrated circuit are disclosed. According to an embodiment, a method for analyzing a timing design of an integrated circuit comprises: providing an initial static timing analysis of the integrated circuit; selecting a static timing test with respect to a static timing test point based on the initial static timing analysis; selecting a timing path leading to the static timing test point for the static timing test; determining an integrated slack path variability for the timing path based on a joint probability distribution of at least one statistically independent parameter; and analyzing the timing design based on the integrated slack path variability.

    摘要翻译： 公开了用于分析集成电路的定时设计的方法，系统和计算机程序产品。 根据实施例，用于分析集成电路的定时设计的方法包括：提供集成电路的初始静态时序分析; 基于初始静态时序分析，选择静态定时测试点的静态定时测试; 选择通过静态定时测试的静态定时测试点的定时路径; 基于至少一个统计学独立参数的联合概率分布来确定所述定时路径的综合松弛路径可变性; 并基于综合的松弛路径变异性分析时序设计。

    SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE
    33.
    发明申请
    SYSTEM AND METHOD FOR GENERATING AT-SPEED STRUCTURAL TESTS TO IMPROVE PROCESS AND ENVIRONMENTAL PARAMETER SPACE COVERAGE 有权
    用于产生速度快速结构测试以改进过程和环境参数空间覆盖的系统和方法

    公开(公告)号：US20090119629A1

    公开(公告)日：2009-05-07

    申请号：US11934146

    申请日：2007-11-02

    申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F11/24 ,  G01R31/31835

    摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

    摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage
    34.
    发明授权
    System and method for generating at-speed structural tests to improve process and environmental parameter space coverage 有权
    用于生成高速结构测试以改进过程和环境参数空间覆盖的系统和方法

    公开(公告)号：US07856607B2

    公开(公告)日：2010-12-21

    申请号：US11934146

    申请日：2007-11-02

    申请人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    发明人： Gary D. Grise ,  Peter A. Habitz ,  Vikram Iyengar ,  David E. Lackey ,  Chandramouli Visweswariah ,  Vladimir Zolotov

    IPC分类号： G06F17/50

    CPC分类号： G06F11/24 ,  G01R31/31835

    摘要： A system for enhancing the practicability of at-speed structural testing (ASST). In one embodiment, the system includes first means for performing statistical timing analysis on a design of logic circuitry. A second means performs a criticality analysis on the logic circuitry as a function of the statistical timing analysis so as to determine a criticality probability for each node of the logic circuitry. A third means selects nodes of the logic circuitry as a function of the criticality analysis. A fourth means selects timing paths as a function of the criticality probabilities of the selected nodes. A fifth means generates an ASST pattern for each of the selected timing paths. A sixth mean is provided to perform ASST on a fabricated instantiation of the design at functional speed using the generated ASST pattern.

    摘要翻译： 一种提高高速结构测试（ASST）实用性的系统。 在一个实施例中，系统包括用于对逻辑电路的设计执行统计时序分析的第一装置。 第二种方法是根据统计时序分析对逻辑电路执行关键性分析，以确定逻辑电路的每个节点的临界概率。 第三种方法是选择逻辑电路的节点作为关键性分析的函数。 第四种装置根据所选节点的临界概率来选择定时路径。 第五装置为每个所选定时路径生成ASST模式。 提供了第六个平均值，以使用所生成的ASST模式在功能速度上对制造的设计实例化执行ASST。

    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT
    35.
    发明申请
    CHIP DESIGN AND FABRICATION METHOD OPTIMIZED FOR PROFIT 有权
    芯片设计和优化方法优化

    公开(公告)号：US20100293512A1

    公开(公告)日：2010-11-18

    申请号：US12467326

    申请日：2009-05-18

    申请人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    发明人： Nathan Buck ,  Howard H. Chen ,  James P. Eckhardt ,  Eric A. Foreman ,  James C. Gregerson ,  Peter A. Habitz ,  Susan K. Lichtensteiger ,  Chandramouli Visweswariah ,  Tad J. Wilder

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5045 ,  G06F17/5031

    摘要： Disclosed is a computer-implemented method for designing a chip to optimize yielding parts in different bins as a function of multiple diverse metrics and further to maximize the profit potential of the resulting chip bins. The method separately calculates joint probability distributions (JPD), each JPD being a function of a different metric (e.g., performance, power consumption, etc.). Based on the JPDs, corresponding yield curves are generated. A profit function then reduces the values of all of these metrics (e.g., performance values, power consumption values, etc.) to a common profit denominator (e.g., to monetary values indicating profit that may be associated with a given metric value). The profit function and, more particularly, the monetary values can be used to combine the various yield curves into a combined profit-based yield curve from which a profit model can be generated. Based on this profit model, changes to the chip design can be made in order to optimize yield as a function of all of the diverse metrics (e.g., performance, power consumption, etc.) and further to maximize the profit potential of the resulting chips.

    摘要翻译： 公开了一种计算机实现的方法，用于设计芯片以优化不同仓中的产量部分作为多个不同度量的函数，并进一步最大化所得到的芯片仓的利润潜力。 该方法分别计算联合概率分布（JPD），每个JPD是不同度量（例如，性能，功耗等）的函数。 基于JPD，生成相应的收益率曲线。 利润函数然后将所有这些度量（例如，绩效值，功耗值等）的值减小到公共利润分母（例如，指示可能与给定度量值相关联的利润的货币值）。 更具体地说，利润函数，尤其是货币价值可用于将各种收益率曲线组合成基于利润的收益率曲线，从中可以产生利润模型。 基于这种利润模型，可以对芯片设计进行改变，以便根据所有不同的指标（例如性能，功耗等）来优化产量，并进一步最大化所得芯片的利润潜力 。