公开(公告)号：US07075150B2

公开(公告)日：2006-07-11

申请号：US10725849

申请日：2003-12-02

申请人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

发明人： Diane C. Boyd ,  Bruce B. Doris ,  Meikei Ieong ,  Devendra K. Sadana

IPC分类号： H01L27/01

CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78684

摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

公开(公告)号：US07056782B2

公开(公告)日：2006-06-06

申请号：US10786901

申请日：2004-02-25

申请人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

发明人： Ricky S. Amos ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Richard D. Kaplan ,  Jakub T. Kedzierski ,  Victor Ku ,  Woo-Hyeong Lee ,  Ying Li ,  Anda C. Mocuta ,  Vijay Narayanan ,  An L. Steegen ,  Maheswaran Surendra

IPC分类号： H01L21/8238

CPC分类号： H01L21/76897 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823835 ,  H01L29/66545 ,  H01L29/6656

摘要： The present invention provides a complementary metal oxide semiconductor integration process whereby a plurality of silicided metal gates are fabricated atop a gate dielectric. Each silicided metal gate that is formed using the integration scheme of the present invention has the same silicide metal phase and substantially the same height, regardless of the dimension of the silicide metal gate. The present invention also provides various methods of forming a CMOS structure having silicided contacts in which the polySi gate heights are substantially the same across the entire surface of a semiconductor structure.

公开(公告)号：US06846734B2

公开(公告)日：2005-01-25

申请号：US10300165

申请日：2002-11-20

申请人： Ricky Amos ,  Katayun Barmak ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub Tadeusz Kedzierski

发明人： Ricky Amos ,  Katayun Barmak ,  Diane C. Boyd ,  Cyril Cabral, Jr. ,  Meikei Leong ,  Thomas S. Kanarsky ,  Jakub Tadeusz Kedzierski

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/823835 ,  H01L21/28097 ,  H01L21/823842 ,  H01L21/84 ,  H01L29/66545

摘要： Methods of forming complementary metal oxide semiconductor (CMOS) devices having multiple-threshold voltages which are easily tunable are provided. Total salicidation with a metal bilayer (representative of the first method of the present invention) or metal alloy (representative of the second method of the present invention) is provided. CMOS devices having multiple-threshold voltages provided by the present methods are also described.

摘要翻译： 提供了形成具有易于调节的多阈值电压的互补金属氧化物半导体（CMOS）器件的方法。 提供了用金属双层（代表本发明的第一种方法）或金属合金（代表本发明的第二种方法）的总的水杨酸化。 还描述了通过本方法提供的具有多阈值电压的CMOS器件。