公开(公告)号：US07033950B2

公开(公告)日：2006-04-25

申请号：US10324564

申请日：2002-12-19

申请人： J. Neil Merrett ,  Tamara Isaacs-Smith ,  David C. Sheridan ,  John R. Williams

发明人： J. Neil Merrett ,  Tamara Isaacs-Smith ,  David C. Sheridan ,  John R. Williams

IPC分类号： H01L21/302

CPC分类号： H01L29/0615 ,  H01L21/0465 ,  H01L29/1608 ,  Y10S438/931

摘要： A graded junction termination extension in a silicon carbide (SiC) semiconductor device and method of its fabrication using ion implementation techniques is provided for high power devices. The properties of silicon carbide (SiC) make this wide band gap semiconductor a promising material for high power devices. This potential is demonstrated in various devices such as p-n diodes, Schottky diodes, bipolar junction transistors, thyristors, etc. These devices require adequate and affordable termination techniques to reduce leakage current and increase breakdown voltage in order to maximize power handling capabilities. The graded junction termination extension disclosed is effective, self-aligned, and simplifies the implementation process.

公开(公告)号：US08202772B2

公开(公告)日：2012-06-19

申请号：US12896130

申请日：2010-10-01

申请人： David C. Sheridan ,  Andrew P. Ritenour

发明人： David C. Sheridan ,  Andrew P. Ritenour

IPC分类号： H01L21/82 ,  H01L29/24

CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）。 这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。 侧壁可以垂直于基板表面形成5°或更大的角度。 这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。 可以使用正常（即0°）或接近正常的入射离子注入来制造器件。 这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况

公开(公告)号：US20090278137A1

公开(公告)日：2009-11-12

申请号：US12170599

申请日：2008-07-10

申请人： David C. Sheridan ,  Andrew Ritenour

发明人： David C. Sheridan ,  Andrew Ritenour

IPC分类号： H01L29/24

CPC分类号： H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7832 ,  H01L29/8083 ,  H01L29/8122

摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

公开(公告)号：US08659057B2

公开(公告)日：2014-02-25

申请号：US13112075

申请日：2011-05-20

申请人： Andrew Ritenour ,  David C. Sheridan

发明人： Andrew Ritenour ,  David C. Sheridan

IPC分类号： H01L29/15 ,  H01L31/0312

CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/7722

摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

摘要翻译： 描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。 为了保持良好的高电压性能（即低DIBL），器件栅极可以自对准到源极的0.5μm以内，同时在反向偏压下减小栅极 - 源极结泄漏。 该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。 还描述了制造该装置的方法。

公开(公告)号：US08507335B2

公开(公告)日：2013-08-13

申请号：US13108505

申请日：2011-05-16

申请人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

发明人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

IPC分类号： H01L21/205

CPC分类号： H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

公开(公告)号：US20110291107A1

公开(公告)日：2011-12-01

申请号：US13112075

申请日：2011-05-20

申请人： Andrew Ritenour ,  David C. Sheridan

发明人： Andrew Ritenour ,  David C. Sheridan

IPC分类号： H01L29/161 ,  H01L21/337 ,  H01L29/808

CPC分类号： H01L29/8083 ,  H01L29/0657 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/7722

摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.

摘要翻译： 描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。 为了保持良好的高电压性能（即低DIBL），器件栅极可以自对准至0.5μm以内，同时减少反向偏压下的栅 - 源结泄漏。 该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。 还描述了制造该装置的方法。

公开(公告)号：US07994548B2

公开(公告)日：2011-08-09

申请号：US12170599

申请日：2008-07-10

申请人： David C. Sheridan ,  Andrew Ritenour

发明人： David C. Sheridan ,  Andrew Ritenour

IPC分类号： H01L29/76

CPC分类号： H01L29/1058 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/475 ,  H01L29/7832 ,  H01L29/8083 ,  H01L29/8122

摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

公开(公告)号：US20090278177A1

公开(公告)日：2009-11-12

申请号：US12117121

申请日：2008-05-08

申请人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

发明人： Igor Sankin ,  David C. Sheridan ,  Joseph Neil Merrett

IPC分类号： H01L49/00 ,  H01L21/425

CPC分类号： H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

公开(公告)号：US08513675B2

公开(公告)日：2013-08-20

申请号：US13476304

申请日：2012-05-21

申请人： David C. Sheridan ,  Andrew P. Ritenour

发明人： David C. Sheridan ,  Andrew P. Ritenour

IPC分类号： H01L29/24 ,  H01L49/00

CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）。 这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。 侧壁可以垂直于基板表面形成5°或更大的角度。 这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。 可以使用正常（即0°）或接近正常的入射离子注入来制造器件。 这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况下制造。

公开(公告)号：US08058655B2

公开(公告)日：2011-11-15

申请号：US12613065

申请日：2009-11-05

申请人： David C. Sheridan ,  Andrew P. Ritenour

发明人： David C. Sheridan ,  Andrew P. Ritenour

IPC分类号： H01L29/24 ,  H01L49/00

CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068

摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of

摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）。 这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。 侧壁可以垂直于基板表面形成5°或更大的角度。 这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。 可以使用正常（即0°）或接近正常的入射离子注入来制造器件。 这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况