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    Methods of forming features of integrated circuits using modified buried layers
    2.
    发明授权
    Methods of forming features of integrated circuits using modified buried layers 失效
    使用改进的埋层形成集成电路特征的方法

    公开(公告)号：US06346446B1

    公开(公告)日：2002-02-12

    申请号：US09317239

    申请日：1999-05-24

    申请人： Andrew P. Ritenour

    发明人： Andrew P. Ritenour

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78621 ,  H01L29/78648

    摘要： Self-aligned features of double sided integrated circuits are formed by modifying a buried layer in an integrated circuit substrate to provide a modified buried layer. The modified buried layer can be formed using ion implantation. In particular, a first feature on an upper surface of the integrated circuit is used as a mask during an ion implantation step. The first feature on the upper surface shields an underlying portion of the modified buried layer from the ion implantation, thereby preventing the modification of the underlying portion. The integrated circuit is flipped over and a lower surface of the integrated circuit is processed wherein a second feature is formed on the lower surface using the modified buried layer as a mask. Accordingly, the second feature is formed self-aligned to the modified buried layer and to the first feature.

    摘要翻译： 双面集成电路的自对准特征是通过修改集成电路衬底中的掩埋层来形成改进的掩埋层。 可以使用离子注入形成修饰的掩埋层。 特别地，在离子注入步骤期间，将集成电路的上表面上的第一特征用作掩模。 上表面上的第一特征将修饰的掩埋层的下面的部分从离子注入屏蔽，从而防止下面的部分的修改。 集成电路被翻转，并且处理集成电路的下表面，其中使用修改的掩埋层作为掩模在下表面上形成第二特征。 因此，第二特征形成为与修改的掩埋层自对准并且与第一特征形成自对准。

    VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING
    4.
    发明申请
    VERTICAL JUNCTION FIELD EFFECT TRANSISTORS HAVING SLOPED SIDEWALLS AND METHODS OF MAKING 有权
    具有斜面的垂直连接场效应晶体管及其制造方法

    公开(公告)号：US20110020991A1

    公开(公告)日：2011-01-27

    申请号：US12896130

    申请日：2010-10-01

    申请人： David C. SHERIDAN ,  Andrew P. RITENOUR

    发明人： David C. SHERIDAN ,  Andrew P. RITENOUR

    IPC分类号： H01L21/337

    CPC分类号： H01L29/8083 ,  H01L21/047 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/66068

    摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs). The devices have raised regions with sloped sidewalls which taper inward. The sidewalls can form an angle of 5° or more from vertical to the substrate surface. The devices can have dual-sloped sidewalls in which a lower portion of the sidewalls forms an angle of 5° or more from vertical and an upper portion of the sidewalls forms an angle of

    摘要翻译： 对半导体装置及其制造方法进行说明。 器件可以是结型场效应晶体管（JFET）。 这些装置具有向内倾斜的具有倾斜侧壁的凸起区域。 侧壁可以垂直于基板表面形成5°或更大的角度。 这些装置可以具有双斜面侧壁，其中侧壁的下部形成垂直方向为5°或更大的角度，并且侧壁的上部部分与垂直方向形成<5°的角度。 可以使用正常（即0°）或接近正常的入射离子注入来制造器件。 这些器件具有相对均匀的侧壁掺杂，并且可以在没有成角度注入的情况下制造。

    Processes for forming backplanes for electro-optic displays
    5.
    发明授权
    Processes for forming backplanes for electro-optic displays 有权
    用于形成电光显示器背板的工艺

    公开(公告)号：US07785988B2

    公开(公告)日：2010-08-31

    申请号：US12243411

    申请日：2008-10-01

    申请人： Karl R. Amundson ,  Guy M. Danner ,  Gregg M. Duthaler ,  Peter T. Kazlas ,  Yu Chen ,  Kevin L. Denis ,  Nathan R. Kane ,  Andrew P. Ritenour

    发明人： Karl R. Amundson ,  Guy M. Danner ,  Gregg M. Duthaler ,  Peter T. Kazlas ,  Yu Chen ,  Kevin L. Denis ,  Nathan R. Kane ,  Andrew P. Ritenour

    IPC分类号： H01L21/30

    CPC分类号： H01L27/1266 ,  B60C23/04 ,  G02F1/133305 ,  G02F1/1362 ,  G02F1/167 ,  G02F2001/13613 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/78603

    摘要： A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors. The invention also provides a process for forming a diode on a substrate by depositing on the substrate a first conductive layer, and a second patterned conductive layer and a patterned dielectric layer over parts of the first conductive layer, and etching the first conductive layer using the second conductive layer and dielectric layer as an etch mask. Finally, the invention provides a process for driving an impulse-sensitive electro-optic display.

    摘要翻译： 通过将基板固定到刚性载体上，形成非线性元件，然后将柔性基板与载体分离，在柔性基板上形成非线性元件。 该方法允许柔性基底在旨在处理刚性基底的常规晶圆中进行加工。 在第二种方法中，通过形成栅电极，沉积介电层，半导体层和导电层，在绝缘基板上形成晶体管，图案化导电层以形成源极，漏极和像素电极，覆盖该沟道区 具有耐蚀刻材料的合成晶体管和使用耐蚀刻材料和导电层作为掩模的蚀刻，蚀刻基本上延伸通过相邻晶体管之间的半导体层。 本发明还提供了一种通过在衬底上沉积第一导电层以及第二图案化导电层和在第一导电层的部分上的图案化电介质层在衬底上形成二极管的工艺，并且使用 第二导电层和介电层作为蚀刻掩模。 最后，本发明提供一种驱动脉冲敏感电光显示器的方法。

    PROCESSES FOR FORMING BACKPLANES FOR ELECTRO-OPTIC DISPLAYS
    8.
    发明申请
    PROCESSES FOR FORMING BACKPLANES FOR ELECTRO-OPTIC DISPLAYS 有权
    用于形成电光显示器的背板的方法

    公开(公告)号：US20090029527A1

    公开(公告)日：2009-01-29

    申请号：US12243411

    申请日：2008-10-01

    申请人： Karl R. Amundson ,  Guy M. Danner ,  Gregg M. Duthaler ,  Peter T. Kazlas ,  Yu Chen ,  Kevin L. Denis ,  Nathan R. Kane ,  Andrew P. Ritenour

    发明人： Karl R. Amundson ,  Guy M. Danner ,  Gregg M. Duthaler ,  Peter T. Kazlas ,  Yu Chen ,  Kevin L. Denis ,  Nathan R. Kane ,  Andrew P. Ritenour

    IPC分类号： H01L21/64

    CPC分类号： H01L27/1266 ,  B60C23/04 ,  G02F1/133305 ,  G02F1/1362 ,  G02F1/167 ,  G02F2001/13613 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/66765 ,  H01L29/78603

    摘要： A non-linear element is formed on a flexible substrate by securing the substrate to a rigid carrier, forming the non-linear element, and then separating the flexible substrate from the carrier. The process allows flexible substrates to be processed in a conventional fab intended to process rigid substrates. In a second method, a transistor is formed on a insulating substrate by forming gate electrodes, depositing a dielectric layer, a semiconductor layer and a conductive layer, patterning the conductive layer to form source, drain and pixel electrodes, covering the channel region of the resultant transistor with an etch-resistant material and etching using the etch-resistant material and the conductive layer as a mask, the etching extending substantially through the semiconductor layer between adjacent transistors. The invention also provides a process for forming a diode on a substrate by depositing on the substrate a first conductive layer, and a second patterned conductive layer and a patterned dielectric layer over parts of the first conductive layer, and etching the first conductive layer using the second conductive layer and dielectric layer as an etch mask. Finally, the invention provides a process for driving an impulse-sensitive electro-optic display.

    摘要翻译： 通过将基板固定到刚性载体上，形成非线性元件，然后将柔性基板与载体分离，在柔性基板上形成非线性元件。 该方法允许柔性基底在旨在处理刚性基底的常规晶圆中进行加工。 在第二种方法中，通过形成栅电极，沉积介电层，半导体层和导电层，在绝缘基板上形成晶体管，图案化导电层以形成源极，漏极和像素电极，覆盖该沟道区 具有耐蚀刻材料的合成晶体管和使用耐蚀刻材料和导电层作为掩模的蚀刻，蚀刻基本上延伸通过相邻晶体管之间的半导体层。 本发明还提供了一种通过在衬底上沉积第一导电层以及第二图案化导电层和在第一导电层的部分上的图案化电介质层在衬底上形成二极管的工艺，并且使用 第二导电层和介电层作为蚀刻掩模。 最后，本发明提供一种驱动脉冲敏感电光显示器的方法。