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31.发明授权
公开(公告)号：US5850553A
公开(公告)日：1998-12-15
申请号：US747054
申请日：1996-11-12
IPC分类号： G06F9/45
摘要： A compiler technique for reducing the number of executed branches in a code sequence. Multiple condition branch instructions in a program sequence are replaced with a single combined conditional branch instruction thereby eliminating the time-consuming execution of multiple branch instructions by a target processor.
摘要翻译： 一种用于减少代码序列中执行分支数量的编译器技术。 程序序列中的多条件分支指令被替换为单个组合条件分支指令，从而消除了目标处理器对多个分支指令的耗时执行。
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公开(公告)号：US20120030345A1
公开(公告)日：2012-02-02
申请号：US12848664
申请日：2010-08-02
IPC分类号： G06F15/173 , G06F9/455
CPC分类号： G06F1/3203 , G06F9/5094 , Y02D10/22
摘要： The present disclosure includes a system and method for managing network and server power. In an example of managing network and server power according to the present disclosure, routing network traffic is routed onto a number of core networks based on core network statistics, capacity requirements are determined based on core network statistics for the number of core networks and for a number of servers operating a number of virtual machines on the number of core networks, wherein the number of core networks include a number of core switches and a number of edge switches, and the capacity is set for the number of core switches based on the capacity requirements for the number of core networks and for the number of servers based on the capacity requirements for the number of servers.
摘要翻译： 本公开包括用于管理网络和服务器功率的系统和方法。 在根据本公开的管理网络和服务器电力的示例中，基于核心网络统计信息将路由网络业务路由到多个核心网络，基于核心网络的核心网络统计确定容量要求，并且对于 核心网络数量的多个虚拟机的服务器数量，其中核心网络的数量包括多个核心交换机和多个边缘交换机，并且基于容量为核心交换机的数量设置容量 基于服务器数量的容量要求，核心网络数量和服务器数量的要求。
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公开(公告)号：US07984242B2
公开(公告)日：2011-07-19
申请号：US12476109
申请日：2009-06-01
IPC分类号： G06F12/00
CPC分类号： G06F9/52
摘要： A barrier for synchronizing program threads for a plurality of processors includes a filter configured to be coupled to a plurality of processors executing a plurality of threads to be synchronized. The filter is configured to monitor and selectively block fill requests for instruction cache lines. A method for synchronizing program threads for a plurality of processors includes configuring a filter to monitor and selectively block fill requests for instruction cache lines for a plurality of processors executing a plurality of threads to be synchronized.
摘要翻译： 用于同步用于多个处理器的程序线程的屏障包括被配置为耦合到执行要同步的多个线程的多个处理器的滤波器。 过滤器被配置为监视和选择性地阻止指令高速缓存行的填充请求。 一种用于同步多个处理器的程序线程的方法包括配置一个过滤器以监视并选择性地阻止执行要同步的多个线程的多个处理器的指令高速缓存线的填充请求。
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公开(公告)号：US07296136B1
公开(公告)日：2007-11-13
申请号：US10861710
申请日：2004-06-04
CPC分类号： G06F12/0859 , G06F9/30043 , G06F9/30072 , G06F9/3017 , G06F9/355 , G06F12/0897 , G06F12/1027
摘要： According to an exemplary embodiment of the present invention, a method for loading data from at least one memory device includes the steps of loading a first value from a first memory location of the at least one memory device, determining a second memory location based on the first value and loading a second value from the second memory location of the at least one memory device, wherein the step of loading a first value is performed by a first processing unit and wherein the steps of determining a second memory location and loading a second value are performed by at least one other processing unit.
摘要翻译： 根据本发明的示例性实施例，一种用于从至少一个存储设备加载数据的方法包括以下步骤：从所述至少一个存储器设备的第一存储器位置加载第一值，基于所述至少一个存储器设备确定第二存储器位置 第一值并从所述至少一个存储器件的第二存储器位置加载第二值，其中由第一处理单元执行加载第一值的步骤，并且其中确定第二存储器位置并加载第二值的步骤 由至少一个其他处理单元执行。
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公开(公告)号：US07194609B2
公开(公告)日：2007-03-20
申请号：US10214990
申请日：2002-08-08
IPC分类号： G06F15/163
CPC分类号： G06F9/3891 , G06F9/30058 , G06F9/30189 , G06F9/3804 , G06F9/3824 , G06F9/3828 , G06F9/3836 , G06F9/3842 , G06F9/3851 , G06F9/3885
摘要： The invention is a system and method for executing programs. The invention involves a plurality of processing elements, wherein a processing element of the plurality of processing elements generates a branch command. The invention uses a programmable network that transports the branch command from the processing element to one of a first destination processing element by a first programmed transport route and a second destination processing element by a second programmed transport route. The branch command is received and processed by one of the first destination processing element and the second destination processing element, and is not processed by the other of the first processing element and the second processing element.
摘要翻译： 本发明是用于执行程序的系统和方法。 本发明涉及多个处理元件，其中多个处理元件的处理元件产生分支命令。 本发明使用可编程网络，该可编程网络通过第一编程传输路由将第二目的地处理单元从第一目的地处理单元传送到处理单元中的分支命令，而第二目的地处理单元通过第二编程传输路由传输分支命令。 分支命令由第一目的地处理元件和第二目的地处理元件之一接收和处理，并且不被第一处理元件和第二处理元件中的另一个处理。
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36.发明授权System and method for independent branching in systems with plural processing elements 有权具有多个处理元件的系统中的独立分支的系统和方法公开(公告)号：US07000091B2
公开(公告)日：2006-02-14
申请号：US10215095
申请日：2002-08-08
IPC分类号： G06F15/76
CPC分类号： G06F9/3887 , G06F9/3836
摘要： The invention is a system and method for executing a program that comprises a plurality of basic blocks on a computer system that comprises a plurality of processing elements. The invention generates a branch instruction by one processing element of the plurality of processing elements, sends the branch instruction to the plurality of processing elements. The invention then independently branches to a target of the branch instruction by each of the processing elements of the plurality of processing elements when each processing element receives the sent branch instruction. At least one processing element of the plurality of processing elements receives the branch instruction at a time later than another processing element of the plurality of processing elements.
摘要翻译： 本发明是一种用于执行程序的系统和方法，该程序包括包括多个处理元件的计算机系统上的多个基本块。 本发明由多个处理单元的一个处理单元生成分支指令，将分支指令发送给多个处理单元。 然后，当每个处理元件接收发送的分支指令时，本发明独立地分支到多个处理元件的每个处理元件的分支指令的目标。 多个处理元件中的至少一个处理元件在比多个处理元件中的另一个处理元件晚的时间接收分支指令。
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