公开(公告)号：US11031472B2

公开(公告)日：2021-06-08

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US10937869B2

公开(公告)日：2021-03-02

申请号：US16147227

申请日：2018-09-28

Applicant: General Electric Company

Inventor： William Gregg Hawkins ,  Reza Ghandi ,  Christopher Bauer ,  Shaoxin Lu

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/78 ,  H01L21/306 ,  H01L21/04 ,  H01L21/02 ,  H01L29/423

Abstract: The subject matter disclosed herein relates to wide band gap semiconductor power devices and, more specifically, to high-energy implantation masks used in forming silicon carbide (SiC) power devices, such as charge balanced (CB) SiC power devices. An intermediate semiconductor device structure includes a SiC substrate layer having a first conductivity type and silicon carbide (SiC) epitaxial (epi) layer having the first conductivity type disposed on the SiC substrate layer. The intermediate device structure also includes a silicon high-energy implantation mask (SiHEIM) disposed directly on a first portion of the SiC epi layer and having a thickness between 5 micrometers (μm) and 20 μm. The SiHEIM is configured to block implantation of the first portion of the SiC epi layer during a high-energy implantation process having an implantation energy greater than 500 kiloelectron volts (keV).

公开(公告)号：US20200212182A1

公开(公告)日：2020-07-02

申请号：US16282145

申请日：2019-02-21

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A silicon carbide (SiC) semiconductor device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a plurality of CB regions having a second conductivity type. The SiC semiconductor device may further include a device epi layer having the first conductivity type disposed on the CB layer. The device epi layer may include a plurality of regions having the second conductivity type. Additionally, the SiC semiconductor device may include an ohmic contact disposed on the device epi layer and a rectifying contact disposed on the device epi layer. A field-effect transistor (FET) of the device may include the ohmic contact, and a diode of the device may include the rectifying contact, where the diode and the FET are integrated in the device.

公开(公告)号：US10608079B2

公开(公告)日：2020-03-31

申请号：US15890077

申请日：2018-02-06

Applicant: General Electric Company

Inventor： Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/02 ,  H01L27/092 ,  H01L21/265 ,  H01L21/324 ,  H01L27/088 ,  H01L21/761 ,  H01L21/82 ,  H01L27/06 ,  H01L21/8234

Abstract: An integrated circuit includes a silicon carbide (SiC) epitaxial layer disposed on a SiC layer, wherein the SiC epitaxial layer has a first conductivity-type and the SiC layer has a second conductivity-type that is opposite to the first conductivity-type. The integrated circuit also includes a junction isolation feature disposed in the SiC epitaxial layer and having the second conductivity-type. The junction isolation feature extends vertically through a thickness of the SiC epitaxial layer and contacts the SiC layer, and wherein the junction isolation feature has a depth of at least about 2 micrometers (μm).

公开(公告)号：US10600649B2

公开(公告)日：2020-03-24

申请号：US15953037

申请日：2018-04-13

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC: H01L21/04 ,  H01L29/36 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/16 ,  H01L29/10

Abstract: A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US10586846B2

公开(公告)日：2020-03-10

申请号：US16010531

申请日：2018-06-18

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L21/265 ,  H01L29/20 ,  H01L21/266 ,  H01L29/78

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US10014388B1

公开(公告)日：2018-07-03

申请号：US15398489

申请日：2017-01-04

Applicant: General Electric Company

Inventor： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/74 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861 ,  H01L29/78

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US09704949B1

公开(公告)日：2017-07-11

申请号：US15199262

申请日：2016-06-30

Applicant: General Electric Company

Inventor： Reza Ghandi ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld

IPC: H01L29/16 ,  H01L29/06 ,  H01L29/872 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0634 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/47 ,  H01L29/6606 ,  H01L29/872

Abstract: A charge-balanced (CB) diode may include one or more CB layers. Each CB layer may include an epitaxial layer having a first conductivity type and a plurality of buried regions having a second conductivity type. Additionally, the CB diode may include an upper epitaxial layer having the first conductivity type that is disposed adjacent to an uppermost CB layer of the one or more CB layers. The upper epitaxial layer may also include a plurality of junction barrier (JBS) implanted regions having the second conductivity type. Further, the CB diode may include a Schottky contact disposed adjacent to the upper epitaxial layer and the plurality of JBS implanted regions.