公开(公告)号：US11233157B2

公开(公告)日：2022-01-25

申请号：US16147210

申请日：2018-09-28

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC分类号： H01L29/812 ,  H01L29/80 ,  H01L21/04 ,  H01L29/66 ,  H01L29/16

摘要： A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

公开(公告)号：US20180190791A1

公开(公告)日：2018-07-05

申请号：US15398489

申请日：2017-01-04

申请人： General Electric Company

发明人： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC分类号： H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861

CPC分类号： H01L29/66537 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7424 ,  H01L29/7811 ,  H01L29/8618

摘要： The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US10002920B1

公开(公告)日：2018-06-19

申请号：US15379214

申请日：2016-12-14

申请人： General Electric Company

发明人： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

摘要： The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US11245003B2

公开(公告)日：2022-02-08

申请号：US16517193

申请日：2019-07-19

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

摘要： A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US20210288180A1

公开(公告)日：2021-09-16

申请号：US17338337

申请日：2021-06-03

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L21/04 ,  H01L29/08

摘要： A charge balanced (CB) trench-metal-oxide-semiconductor field-effect transistor (MOSFET) device may include a charge balanced (CB) layer defined within a first epitaxial (epi) layer that has a first conductivity type. The CB layer may include charge balanced (CB) regions that has a second conductivity type. The CB trench-MOSFET device may include a device layer defined in a second epi layer and having the first conductivity type, where the device layer is disposed on the CB layer. The device layer may include a source region, a base region, a trench feature, and a shield region having the second conductivity type disposed at a bottom surface of the trench feature. The device layer may also include a charge balanced (CB) bus region having the second conductivity type that extends between and electrically couples the CB regions of the CB layer to at least one region of the device layer having the second conductivity type.

公开(公告)号：US11069772B2

公开(公告)日：2021-07-20

申请号：US16221034

申请日：2018-12-14

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Reza Ghandi ,  Alexander Viktorovich Bolotnikov ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L29/417 ,  H01L29/423

摘要： Aspects of the present disclosure are directed toward designs and methods of manufacturing semiconductor devices, such as semiconductor charge balanced (CB) devices or semiconductor super-junction (SJ) devices. The disclosed designs and methods are useful in the manufacture of CB devices, such as planar CB metal-oxide semiconductor field-effect transistor (MOSFET) devices, as well as other devices.

公开(公告)号：US20190088479A1

公开(公告)日：2019-03-21

申请号：US15953037

申请日：2018-04-13

申请人： General Electric Company

发明人： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  Reza Ghandi ,  David Alan Lilienfeld

IPC分类号： H01L21/04 ,  H01L29/16 ,  H01L29/36 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

摘要： A method of manufacturing a semiconductor device including performing a first implantation in a semiconductor layer via ion implantation forming a first implantation region and performing a second implantation in the semiconductor layer via ion implantation forming a second implantation region. The first and second implantation overlap with one another and combine to form a connection region extending into the semiconductor layer by a predefined depth.

公开(公告)号：US20170278924A1

公开(公告)日：2017-09-28

申请号：US15077579

申请日：2016-03-22

申请人： General Electric Company

发明人： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee ,  David Alan Lilienfeld ,  Reza Ghandi

IPC分类号： H01L29/06 ,  H01L21/04 ,  H01L29/808 ,  H01L29/73 ,  H01L29/78 ,  H01L29/16 ,  H01L29/861

CPC分类号： H01L29/0634 ,  H01L21/046 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66136 ,  H01L29/66143 ,  H01L29/66272 ,  H01L29/66909 ,  H01L29/73 ,  H01L29/732 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/808 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/872

摘要： A super junction (SJ) device may include one or more charge balance (CB) layers. Each CB layer may include an epitaxial (epi) layer having a first conductivity type and a plurality of charge balance (CB) regions having a second conductivity type. Additionally, the SJ device may include a connection region having the second conductivity type that extends from a region disposed in a top surface of a device layer of the SJ device to one or more of the CB regions. The connection region may enable carriers to flow directly from the region to the one or more CB regions, which may decrease switching losses of the SJ device.

公开(公告)号：US20220130953A1

公开(公告)日：2022-04-28

申请号：US17572274

申请日：2022-01-10

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC分类号： H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

摘要： A disclosed super-junction (SJ) device includes a first epitaxial (epi) layer that forms a first SJ layer of the SJ device, and includes a second epi layer disposed on the first SJ layer that forms a device layer of the SJ device. An active area of the first and second epi layers includes a first set of SJ pillars comprising a particular doping concentration of a first conductivity type and a second set of SJ pillars comprising the particular doping concentration of a second conductivity type. A termination area of the first and second epi layers has a minimized epi doping concentration of the first conductivity type that is less than the particular doping concentration, and the termination area of the second epi layer includes a plurality of floating regions of the second conductivity type that form a junction termination of the SJ device.

公开(公告)号：US11271076B2

公开(公告)日：2022-03-08

申请号：US16517222

申请日：2019-07-19

申请人： General Electric Company

发明人： Stephen Daley Arthur ,  Victor Mario Torres ,  Michael J. Hartig ,  Reza Ghandi ,  David Alan Lilienfeld ,  Alexander Viktorovich Bolotnikov

IPC分类号： H01L29/15 ,  H01L31/0312 ,  H01L29/06 ,  H01L29/16 ,  H01L21/04 ,  H01L29/66

摘要： The subject matter disclosed herein relates to semiconductor power devices and, more specifically, to junction termination designs for wide-bandgap (e.g., silicon carbide) semiconductor power devices. A disclosed semiconductor device includes a first epitaxial (epi) layer disposed on a substrate layer, wherein a termination area of the first epi layer has a minimized epi doping concentration of a first conductivity type (e.g., n-type). The device also includes a second epi layer disposed on the first epi layer, wherein a termination area of the second epi layer has the minimized epi doping concentration of the first conductivity type and includes a first plurality of floating regions of a second conductivity type (e.g., p-type) that form a first junction termination of the device.