公开(公告)号：US09653454B1

公开(公告)日：2017-05-16

申请号：US15215043

申请日：2016-07-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chien-hsin Lee ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu

IPC: H01L21/336 ,  H01L27/02 ,  H01L29/74 ,  H01L29/66

CPC classification number: H01L27/0255 ,  H01L21/823431 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/66371 ,  H01L29/7408 ,  H01L29/785

Abstract: Methods to forming trigger-voltage tunable cascode transistors for an ESD protection circuit in FinFET IC devices and resulting devices. Embodiments include providing a substrate including adjacent first-type well areas, over the substrate, each pair of first-type well areas separated by a second-type well area; providing one or more junction areas in each first and second type well area, each junction area being a first type or a second type; forming fins, spaced from each other, perpendicular to and over the first and second type junction areas; and forming junction-type devices by forming electrical connections between the first and second type junction areas in the first-type well areas and the substrate, wherein a first-stage junction-type device in a first-type well area includes stacked first and second type junction areas, and wherein the first-stage junction-type device is adjacent a second-type well area including first and second type junction areas.

公开(公告)号：US09177951B2

公开(公告)日：2015-11-03

申请号：US14148221

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L21/306 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract translation: 三维静电放电（ESD）半导体器件与三维非ESD半导体器件一起制造。 例如，ESD二极管和FinFET制造在相同的体半导体衬底上。 衬底合并技术用于衬底的ESD部分中以形成双宽度鳍片，其上可以使ESD器件更大以处理更多的电流。

公开(公告)号：US20150214733A1

公开(公告)日：2015-07-30

申请号：US14682910

申请日：2015-04-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Manjunatha Govinda Prabhu ,  Mahadeva Iyer Natarajan

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: A circuit for electrostatic discharge (ESD) protection is disclosed. The circuit includes multiple transistors that are selectively turned on during an ESD event. An ESD sense circuit detects an ESD event and asserts signals to activate an ESD protection circuit which closes multiple protection transistors to dissipate current during the ESD event. During normal operation of the circuit, the signals are de-asserted, disabling the ESD protection circuit.

Abstract translation: 公开了一种用于静电放电（ESD）保护的电路。 电路包括在ESD事件期间选择性地导通的多个晶体管。 ESD感测电路检测ESD事件并断言信号以激活ESD保护电路，其关闭多个保护晶体管以在ESD事件期间耗散电流。 在电路正常工作期间，信号被取消置位，禁止ESD保护电路。