公开(公告)号：US20080276070A1

公开(公告)日：2008-11-06

申请号：US12176385

申请日：2008-07-20

申请人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F9/312

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

公开(公告)号：US07437543B2

公开(公告)日：2008-10-14

申请号：US11109001

申请日：2005-04-19

申请人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F9/40

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。

公开(公告)号：US20080189519A1

公开(公告)日：2008-08-07

申请号：US12062131

申请日：2008-04-03

申请人： Michael Karl Gschwind ,  Robert Kevin Montoye ,  Brett Olsson ,  John-David Wellman

发明人： Michael Karl Gschwind ,  Robert Kevin Montoye ,  Brett Olsson ,  John-David Wellman

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30101 ,  G06F9/30112 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3885

摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.

摘要翻译： 提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。 一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理固定宽度指令集的固定宽度指令。 固定宽度指令包括不连续的寄存器说明符。

公开(公告)号：US06327651B1

公开(公告)日：2001-12-04

申请号：US09149466

申请日：1998-09-08

申请人： Pradeep Kumar Dubey ,  Brett Olsson ,  Charles Philip Roth ,  Keith Everett Diefendorf ,  Ronald Ray Hochsprung ,  Hunter Ledbetter Scales, III

发明人： Pradeep Kumar Dubey ,  Brett Olsson ,  Charles Philip Roth ,  Keith Everett Diefendorf ,  Ronald Ray Hochsprung ,  Hunter Ledbetter Scales, III

IPC分类号： G06F1500

CPC分类号： G06F7/766 ,  G06F5/015

摘要： A crossbar is implemented within multimedia facilities of a processor to perform vector permute operations, in which the bytes of a source operand are reordered in the target output. The crossbar is then reused for other instructions requiring multiplexing or shifting operations, particularly those in which the size of additional multiplexers or the size and delay of a barrel shifter is significant. A wide shift operation, for example, may be performed with one cycle latency by the crossbar and one additional layer of multiplexers or a small barrel shifter. The crossbar facility thus gets reused with improved performance of the instructions now sharing the crossbar and a reduction in the total area required by a multimedia facility within a processor.

摘要翻译： 在处理器的多媒体设施内实现交叉开关以执行矢量置换操作，其中源操作数的字节在目标输出中重新排序。 然后，交叉开关重新用于需要复用或移位操作的其他指令，特别是其中附加多路复用器的大小或桶形移位器的大小和延迟是显着的那些指令。 例如，可以通过交叉开关和一个附加的多路复用器层或小桶形移位器以一个周期的等待时间来执行宽移位操作。 因此，交叉开关设备被重新使用，现在共享交叉开关的指令的性能得到改善，并且减少处理器内的多媒体设备所需的总面积。

公开(公告)号：US06202130B1

公开(公告)日：2001-03-13

申请号：US09061975

申请日：1998-04-17

申请人： Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Bradford Byron Beavers ,  Bradley G. Burgess ,  Michael Dean Snyder ,  Cathy May ,  Edward John Silha

发明人： Hunter Ledbetter Scales, III ,  Keith Everett Diefendorff ,  Brett Olsson ,  Pradeep Kumar Dubey ,  Ronald Ray Hochsprung ,  Bradford Byron Beavers ,  Bradley G. Burgess ,  Michael Dean Snyder ,  Cathy May ,  Edward John Silha

IPC分类号： G06F1200

CPC分类号： G06F9/30047 ,  G06F9/30101 ,  G06F12/0862 ,  G06F2212/6028

摘要： A data processing system includes a data processor (10) coupled to a memory system having a first memory, such as an L1 data cache (16), arranged with a second memory (such as an L2 cache) at a lower hierarchical level. The data processor (10) prefetches data elements of a vector into the first memory prior to processing such data elements. If a requested data element is not present in the first memory, a load request is issued to the second memory and to lower levels of the memory hierarchy until the requested data element is finally retrieved and stored in the first memory. The data processor (10) continues to prefetch subsequent data elements of the vector by considering the length of the data element and the stride of the vector. In one embodiment, the data processor (10) prefetches the vector into the first memory in response to a single data stream touch load (DST) instruction (100).

摘要翻译： 数据处理系统包括耦合到具有诸如L1数据高速缓存（16）的第一存储器的存储器系统的数据处理器（10），其布置在较低分层级的第二存储器（例如L2高速缓存）。 在处理这些数据元素之前，数据处理器（10）将向量的数据元素预取到第一存储器中。 如果请求的数据元素不存在于第一存储器中，则向第二存储器发出加载请求，并将存储器层级降低到最低限度，直到所请求的数据元素被最终检索并存储在第一存储器中。 数据处理器（10）通过考虑数据元素的长度和向量的步幅继续预取向量的后续数据元素。 在一个实施例中，数据处理器（10）响应于单个数据流接触负载（DST）指令（100）将矢量预取到第一存储器中。

公开(公告)号：US5680338A

公开(公告)日：1997-10-21

申请号：US368172

申请日：1995-01-04

申请人： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson ,  James B. Shearer

发明人： Ramesh Chandra Agarwal ,  Randall Dean Groves ,  Fred G. Gustavson ,  Mark A. Johnson ,  Brett Olsson ,  James B. Shearer

IPC分类号： G06F17/16

CPC分类号： G06F17/16

摘要： In a vector processing system for processing vector calculations utilizing a portion of a vector comprising a plurality of elements, means for receiving a vector and a vector processing command are provided. The vector processing system also includes means for receiving and storing a start-element value and an end-element value. An arithmetic logic unit is coupled to the means for receiving the vector, the means for receiving the vector processing command, and the means for receiving the start-element and end-element values. The arithmetic logic unit also includes means for executing the vector processing command utilizing only one or more of the elements in the vector, which are selected by the start-element value and the end-element value.

摘要翻译： 在使用包括多个元素的向量的一部分来处理向量计算的向量处理系统中，提供了用于接收向量和向量处理命令的装置。 矢量处理系统还包括用于接收和存储起始元素值和终止元素值的装置。 算术逻辑单元耦合到用于接收向量的装置，用于接收向量处理命令的装置和用于接收起始元素和终止元素值的装置。 算术逻辑单元还包括仅利用向量中的一个或多个元素来执行向量处理命令的装置，其由起始元素值和终止元素值选择。

公开(公告)号：US08918623B2

公开(公告)日：2014-12-23

申请号：US13425808

申请日：2012-03-21

申请人： Michael Karl Gschwind ,  Robert K. Montoye ,  Brett Olsson ,  John-David Wellman

发明人： Michael Karl Gschwind ,  Robert K. Montoye ,  Brett Olsson ,  John-David Wellman

IPC分类号： G06F9/30

CPC分类号： G06F9/30185 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/30181

摘要： There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.

摘要翻译： 提供了用于实现具有非连续寄存器文件说明符的指令集架构的方法和计算机程序产品。 一种用于处理指令代码的方法包括使用非连续寄存器规范的非连续寄存器说明符来处理指令集的指令。 该指令包括不连续的寄存器说明符。

公开(公告)号：US20110055517A1

公开(公告)日：2011-03-03

申请号：US12548129

申请日：2009-08-26

申请人： Alexandre E. Eichenberger ,  Michael Karl Gschwind ,  John A. Gunnels ,  Fred Gehrung Gustavson ,  Brett Olsson

发明人： Alexandre E. Eichenberger ,  Michael Karl Gschwind ,  John A. Gunnels ,  Fred Gehrung Gustavson ,  Brett Olsson

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F9/3881 ,  G06F9/3001 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3877 ,  G06F17/16

摘要： A structure (and method) including a plurality of coprocessing units and a controller that selectively loads data for processing on the plurality of coprocessing units, using a compound loading instruction. The compound loading instruction includes a plurality of low-level software instructions that preliminarily processes input data in a manner predetermined to simulate an effect of a single hardware loading instruction that would provide optimal loading of complex matrix data by loading input data in accordance with the effect of multiplying i·i=−1.

摘要翻译： 一种包括多个协处理单元和使用复合加载指令选择性地加载用于处理多个协处理单元的数据的控制器的结构（和方法）。 复合加载指令包括多个低级软件指令，其以预定的方式预先处理输入数据，以模拟单个硬件加载指令的效果，该硬件加载指令将通过根据效果加载输入数据来提供复合矩阵数据的最佳加载 乘以i·i = -1。

公开(公告)号：US07849294B2

公开(公告)日：2010-12-07

申请号：US12023768

申请日：2008-01-31

申请人： Michael K. Gschwind ,  Brett Olsson

发明人： Michael K. Gschwind ,  Brett Olsson

IPC分类号： G06F9/302 ,  G06F9/305

CPC分类号： G06F9/30025 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3016 ,  G06F9/30174 ,  G06F9/30181 ,  G06F9/3885

摘要： Illustrative embodiments determine the data type of the operand being accessed as well as analyze the data value subrange of the input operand data type. If the operand's data type does not match the required format of the instruction being processed, a determination is made as to whether a subrange of data values of the data type of the input operand is supported natively. If the subrange of data values of the input operand is not supported natively, then a format conversion is performed on the data and the instruction may then operate on the data. Otherwise, the data may be operated on directly by the instruction without a format conversion operation and thus, the conversion is not performed.

摘要翻译： 说明性实施例确定被访问的操作数的数据类型以及分析输入操作数数据类型的数据值子范围。 如果操作数的数据类型与正在处理的指令的所需格式不匹配，则确定本地是否支持输入操作数的数据类型的数据值的子范围。 如果本地不支持输入操作数的数据值的子范围，则对数据进行格式转换，然后该指令可以对数据进行操作。 否则，数据可以直接由指令操作，而不进行格式转换操作，因此不进行转换。

公开(公告)号：US20080276071A1

公开(公告)日：2008-11-06

申请号：US12176386

申请日：2008-07-20

申请人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

发明人： Richard William Doing ,  Brett Olsson ,  Kenichi Tsuchiya

IPC分类号： G06F9/312

CPC分类号： G06F9/3804 ,  G06F9/3844

摘要： A method and processor for reducing the fetch time of target instructions of a predicted taken branch instruction. Each entry in a buffer, referred to herein as a “branch target buffer”, may store an address of a branch instruction predicted taken and the instructions beginning at the target address of the branch instruction predicted taken. When an instruction is fetched from the instruction cache, a particular entry in the branch target buffer is indexed using particular bits of the fetched instruction. The address of the branch instruction in the indexed entry is compared with the address of the instruction fetched from the instruction cache. If there is a match, then the instructions beginning at the target address of that branch instruction are dispatched directly behind the branch instruction. In this manner, the fetch time of target instructions of a predicted taken branch instruction is reduced.

摘要翻译： 一种用于减少预测的分支指令的目标指令的获取时间的方法和处理器。 缓冲器中的每个条目（这里称为“分支目标缓冲器”）可以存储预测的分支指令的地址和从预测的分支指令的目标地址开始的指令。 当从指令高速缓存中取出指令时，使用获取的指令的特定位来对分支目标缓冲器中的特定条目进行索引。 将索引条目中的分支指令的地址与从指令高速缓存获取的指令的地址进行比较。 如果有匹配，则从该分支指令的目标地址开始的指令直接在分支指令的后面进行调度。 以这种方式，减少预测的分支指令的目标指令的获取时间。