公开(公告)号：US07921293B2

公开(公告)日：2011-04-05

申请号：US11340181

申请日：2006-01-24

申请人： Michael A. Kozuch ,  James A. Sutton, II ,  David Grawrock ,  Gilbert Neiger ,  Richard A. Uhlig ,  Bradley G. Burgess ,  David I. Poisner ,  Clifford D. Hall ,  Andy Glew ,  Lawrence O. Smith, III ,  Robert George

发明人： Michael A. Kozuch ,  James A. Sutton, II ,  David Grawrock ,  Gilbert Neiger ,  Richard A. Uhlig ,  Bradley G. Burgess ,  David I. Poisner ,  Clifford D. Hall ,  Andy Glew ,  Lawrence O. Smith, III ,  Robert George

IPC分类号： H04L9/00 ,  G06F21/00

CPC分类号： G06F21/57

摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value to establish security verification of secure software within the secure memory environment.

摘要翻译： 描述了在多处理器环境内单方面加载安全操作系统的装置和方法。 该方法包括当检测到当前活动的负载安全区域操作时忽略接收的负载安全区域指令。 否则，响应于接收到的负载安全区域指令，引导存储器保护元件以形成安全存储器环境。 一旦定向，就禁止对一个或多个受保护的存储器区域进行未经授权的读/写访问。 最后，一个或多个受保护的存储器区域的加密散列值作为安全的软件识别值存储在摘要信息库中。 一旦存储，外部代理可以请求访问数字签名的软件标识值以建立安全存储器环境内的安全软件的安全验证。

公开(公告)号：US5392228A

公开(公告)日：1995-02-21

申请号：US161361

申请日：1993-12-06

申请人： Bradley G. Burgess ,  Timothy A. Elliott ,  Christopher H. Olson ,  Terence M. Potter

发明人： Bradley G. Burgess ,  Timothy A. Elliott ,  Christopher H. Olson ,  Terence M. Potter

IPC分类号： G06F7/485 ,  G06F5/01 ,  G06F7/00 ,  G06F7/50 ,  G06F7/76

CPC分类号： G06F7/485 ,  G06F5/012

摘要： A result normalizer (58) for use with an adder (56) generates a mask in two stages that indicates the location of the leading one in the adder result. In the first stage, a leading zero anticipator (68) determines the position to within two digits. In the second stage, a count leading zero indicator (70) determines the position to a single digit. The mask is used to control the number of digits that each stage of a multiplexer array (66) shifts the adder result. The output of the multiplexer array thereby contains a leading one. The result normalizer may be advantageously used in high performance applications such as in a floating point execution unit in a data processor or in digital signal processing systems.

摘要翻译： 与加法器（56）一起使用的结果归一化器（58）在两个阶段中生成指示加法器结果中前导序列的位置的掩码。 在第一阶段，领先的零预测者（68）将位置确定在两位数之内。 在第二阶段中，计数前导零指示符（70）确定位置到单个数字。 该掩码用于控制多路复用器阵列（66）的每个级移位加法器结果的位数。 因此，多路复用器阵列的输出包含一个前导的。 结果归一化器可以有利地用于高性能应用中，例如在数据处理器或数字信号处理系统中的浮点执行单元中。

公开(公告)号：US5072365A

公开(公告)日：1991-12-10

申请号：US457647

申请日：1989-12-27

申请人： Bradley G. Burgess ,  James B. Eifert ,  John P. Dunn

发明人： Bradley G. Burgess ,  James B. Eifert ,  John P. Dunn

IPC分类号： G06F13/28 ,  G06F13/34

CPC分类号： G06F13/34

摘要： A data processing system having a direct memory access controller (DMAC) which can be interrupted with a prioritized signal to vary bus mastership of a communication bus in the system. A prioritized interrupt signal is sent to a CPU when the DMAC has bus mastership. The CPU only informs the DMAC of the highest priority cumulative interrupt priority. With the use of a mask value, the interrupt may be selectively screened by the DMAC so that selective interrupts may remove bus mastership from the DMAC.

公开(公告)号：US20130009697A1

公开(公告)日：2013-01-10

申请号：US13176842

申请日：2011-07-06

申请人： Daniel W. Bailey ,  Aaron S. Rogers ,  James J. Montanaro ,  Bradley G. Burgess ,  Peter J. Hannan

发明人： Daniel W. Bailey ,  Aaron S. Rogers ,  James J. Montanaro ,  Bradley G. Burgess ,  Peter J. Hannan

IPC分类号： G05F3/02

CPC分类号： H03K19/0013 ,  H03K19/0016

摘要： Leakage current is reduced in a plurality of gates coupled between source storage elements and destination storage elements by waking the plurality of gates to allow current flow in response to assertion of any source clock enable signals that enable clocking of the source storage elements. The gates are slept to reduce leakage current in the plurality of gates, in response to assertion of a destination clock enable signal and all of the one or more source clock enable signals being deasserted, the destination clock enable signal enabling clocking of the destination storage elements.

摘要翻译： 通过唤醒多个门以允许电流流动响应于使得能够对源存储元件进行时钟的任何源时钟使能信号的断言，耦合在源存储元件和目的地存储元件之间的多个栅极中的泄漏电流减小。 响应于确定目的地时钟使能信号并且所有一个或多个源时钟使能信号被断言，门被睡眠以减少多个门中的泄漏电流，目的地时钟使能信号使得能够对目的地存储元件进行时钟 。

公开(公告)号：US06477640B1

公开(公告)日：2002-11-05

申请号：US09659401

申请日：2000-09-11

申请人： Jeffrey Pidge Rupley, II ,  Marvin A. Denman ,  Bradley G. Burgess ,  David C. Holloway

发明人： Jeffrey Pidge Rupley, II ,  Marvin A. Denman ,  Bradley G. Burgess ,  David C. Holloway

IPC分类号： G06F1560

CPC分类号： G06F9/3851 ,  G06F9/3844 ,  G06F9/3861

摘要： A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

摘要翻译： 分支预测单元装置和方法使用指令缓冲器（20），完成单元（24）和分支预测单元（BPU）（28）。 指令缓冲器（20）和/或完成单元（24）包含包含有效位和流标识符（SID）位的多个指令条目。 分支预测单元包含多个分支预测缓冲器（28a-28c）。 SID位用于将单元（20和24）中的待执行和执行的指令与位于缓冲器（28a-28c）中的预测分支相关的指令流相关联。 SID位以及与缓冲器（28a-28c）相关联的老化位用于执行有效的分支预测，分支解决/退出和分支错误预测恢复。

公开(公告)号：US5034922A

公开(公告)日：1991-07-23

申请号：US135945

申请日：1987-12-21

申请人： Bradley G. Burgess

发明人： Bradley G. Burgess

IPC分类号： G11C16/26 ,  G11C16/32

CPC分类号： G11C16/26 ,  G11C16/32

摘要： An intelligent electrically erasable, programmable read-only memory achieves improved worst-case read operation latency by allowing for the interruption of write operations by subsequently received read requests. In the preferred embodiment, a state machine controller executes write operations by an iterative process of write pulses and write verify cycles. In addition, cells are erased prior to being written to by a similar iterative process. Both the write operations and the erase operations may be interrupted by read requests received after the write operation has begun execution. To avoid reading incorrect data in the case of a read operation at the same address as an interrupted write operation, a comparator matches read operation addresses with latched write operation addresses and provides the read operation data from a write data latch in the case of a match.

摘要翻译： 智能电可擦除可编程只读存储器通过允许随后接收到的读请求中断写操作来实现改进的最坏情况读操作等待时间。 在优选实施例中，状态机控制器通过写入脉冲和写入验证周期的迭代处理执行写入操作。 此外，在通过类似的迭代过程被写入之前，单元被擦除。 写入操作和擦除操作都可能在写操作开始执行之后被读取请求中断。 为了避免在与中断的写入操作相同的地址处读取操作的情况下读取不正确的数据，比较器将读操作地址与锁存的写操作地址相匹配，并且在匹配的情况下从写数据锁存器提供读操作数据 。

公开(公告)号：US07024555B2

公开(公告)日：2006-04-04

申请号：US10043843

申请日：2001-11-01

申请人： Michael A. Kozuch ,  James A. Sutton, II ,  David Grawrock ,  Gilbert Neiger ,  Richard A. Uhlig ,  Bradley G. Burgess ,  David I. Poisner ,  Clifford D. Hall ,  Andy Glew ,  Lawrence O. Smith, III ,  Robert George

发明人： Michael A. Kozuch ,  James A. Sutton, II ,  David Grawrock ,  Gilbert Neiger ,  Richard A. Uhlig ,  Bradley G. Burgess ,  David I. Poisner ,  Clifford D. Hall ,  Andy Glew ,  Lawrence O. Smith, III ,  Robert George

IPC分类号： G06F1/26

CPC分类号： G06F21/57

摘要： An apparatus and method for unilaterally loading a secure operating system within a multiprocessor environment are described. The method includes disregarding a received load secure region instruction when a currently active load secure region operation is detected. Otherwise, a memory protection element is directed, in response to the received load secure region instruction, to form a secure memory environment. Once directed, unauthorized read/write access to one or more protected memory regions are prohibited. Finally, a cryptographic hash value of the one or more protected memory regions is stored within a digest information repository as a secure software identification value. Once stored, outside agents may request access to a digitally signed software identification value in order to establish security verification of secure software within the secure memory environment.

公开(公告)号：US5500943A

公开(公告)日：1996-03-19

申请号：US442913

申请日：1995-05-17

申请人： Ying-wai Ho ,  Bradley G. Burgess

发明人： Ying-wai Ho ,  Bradley G. Burgess

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/3863

摘要： A data processor has first calculation circuitry (26), a rename buffer (34), and a queue (36). The first calculation circuitry generates a first and a second result from supplied operands and received programmed instructions. The rename buffer is coupled to the first calculation circuitry and stores a series of first results received from the first calculation circuitry. The rename buffer outputs the series of first results to a first predetermined register. The queue is also coupled to the first calculation circuitry and stores a series of second results. The queue outputs the sequence of second results to a second predetermined register in the same the sequence as it received the second results from the first calculation circuitry.

摘要翻译： 数据处理器具有第一计算电路（26），重命名缓冲器（34）和队列（36）。 第一计算电路从提供的操作数和接收的编程指令产生第一和第二结果。 重命名缓冲器耦合到第一计算电路并存储从第一计算电路接收的一系列第一结果。 重命名缓冲器将一系列第一结果输出到第一预定寄存器。 队列还耦合到第一计算电路并存储一系列第二结果。 队列以与从第一计算电路接收到第二结果的顺序相同的顺序将第二结果的序列输出到第二预定寄存器。

公开(公告)号：US5448744A

公开(公告)日：1995-09-05

申请号：US432423

申请日：1989-11-06

申请人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

发明人： James B. Eifert ,  John J. Vaglica ,  James C. Smallwood ,  Mark W. McDermott ,  Hiroyuki Sugiyama ,  William P. LaViolette ,  Bradley G. Burgess

IPC分类号： G06F9/38 ,  G06F9/22 ,  G06F13/10

CPC分类号： G06F9/3877

摘要： An integrated circuit microprocessor has on-board programmable chip select logic. Each of several chip select outputs is individually programmable by means of one or more control register bit fields. For instance, each chip select is asserted for bus cycles within an address range whose starting address and block size are both programmable. In addition, each chip select can be programmed to be active on read cycles only, on write cycles only, or on both read and write cycles. Each chip select can be programmed to be active during interrupt acknowledge cycles only if the interrupt being acknowledged has the same priority level as has been programmed for that chip select. In addition, the timing of the assertion of each chip select is programmable to coincide with either the address strobe or data strobe of the bus cycle. The chip select logic is designed so that it is configured to come out of reset by producing an active chip select signal during the first bus cycle run by the processor following the reset. This chip select is appropriate for selecting a boot ROM, and may later be re-programmed for other use. The chip select logic is capable of supporting cycle-by-cycle dynamic bus sizing by asserting appropriate cycle termination signals. The chip select logic can also insert a programmable number of wait states into a bus cycle to accommodate slow peripherals or can cause a fast termination of a bus cycle to improve the utilization of fast peripherals.

摘要翻译： 集成电路微处理器具有板载可编程芯片选择逻辑。 几个芯片选择输出中的每一个可以通过一个或多个控制寄存器位字段单独编程。 例如，每个芯片选择在起始地址和块大小均可编程的地址范围内被断言用于总线周期。 此外，每个芯片选择都可以被编程为仅在读周期有效，仅在写周期或读周期和写周期。 只有在确认中断与该芯片选择相同的优先级时，每个芯片选择才能在中断确认周期内被编程为有效。 此外，每个芯片选择的断言的定时可编程为与总线周期的地址选通或数据选通一致。 芯片选择逻辑被设计为使得其被配置为在复位之后由处理器运行的第一总线周期期间产生有效芯片选择信号而退出复位。 该芯片选择适用于选择引导ROM，然后可以重新编程以供其他使用。 芯片选择逻辑能够通过断言适当的周期终止信号来支持逐周期动态总线大小调整。 芯片选择逻辑还可以将可编程的等待状态数插入总线周期以适应慢速外设，或者可能导致总线周期的快速终止，从而提高快速外设的利用率。

公开(公告)号：US5361392A

公开(公告)日：1994-11-01

申请号：US033992

申请日：1993-03-19

申请人： Antone L. Fourcroy ,  Mark W. McDermott ,  John P. Dunn ,  Bradley G. Burgess

发明人： Antone L. Fourcroy ,  Mark W. McDermott ,  John P. Dunn ,  Bradley G. Burgess

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F15/78 ,  G06F9/30 ,  G06F9/46 ,  G06F11/20 ,  G06F13/24

CPC分类号： G06F9/30083 ,  G06F1/3203 ,  G06F9/30167

摘要： A digital computing system having a low power mode of operation includes a mechanism for communicating, prior to entering the low power mode, information determinative of which events shall be capable of causing the termination of the low power mode. An integrated circuit microcomputer enters a low power mode in response to executing an LPSTOP instruction. Only reset events and those interrupt events having a priority level sufficiently high to pass an interrupt mask are capable of causing the termination of the low power mode. The LPSTOP instruction causes immediate data to be loaded into a status register, resetting the interrupt mask bits. The interrupt mask is then written, by means of a special bus cycle, into an interrupt mask register in a sub-system within the microcomputer. This subsystem then shuts down the clock signals to the remainder of the microcomputer, leaving only this sub-system active. The active sub-system performs a comparison of the priority levels of received interrupt requests to the interrupt mask during the low power mode. Only if the priority level of an interrupt is sufficiently high are the clock signals resumed, thus terminating the low power mode.

摘要翻译： 具有低功率操作模式的数字计算系统包括用于在进入低功率模式之前通信的信息，该信息确定哪些事件将能够导致低功率模式的终止。 响应于执行LPSTOP指令，集成电路微计算机进入低功率模式。 只有重置事件和具有足够高的优先级才能通过中断掩码的中断事件才能导致低功率模式的终止。 LPSTOP指令将立即数据加载到状态寄存器中，复位中断屏蔽位。 然后通过专用总线周期将中断屏蔽写入微机内的子系统中的中断屏蔽寄存器。 该子系统然后将时钟信号关闭到微计算机的其余部分，只剩下这个子系统。 在低功耗模式下，有源子系统对接收到的中断请求的优先级进行中断屏蔽的比较。 只有当中断的优先级足够高时，恢复时钟信号，从而终止低功耗模式。