公开(公告)号：US20080028805A1

公开(公告)日：2008-02-07

申请号：US11812047

申请日：2007-06-14

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： E05B65/52

CPC分类号： E05B37/0034 ,  E05B37/02 ,  E05B65/5284 ,  Y10T70/409 ,  Y10T70/5009 ,  Y10T70/5058 ,  Y10T70/7141 ,  Y10T70/7147

摘要： A strap lock includes a first snapping member, a second snapping member, a strap, a stop member and a locking mechanism. The second snapping member is detachably secured to the first snapping member. The strap is connected with both the first and the second snapping members to define a loop of a size for enclosing a luggage. The strap includes a movable section capable of being pulled out away from the second snapping member so as to reduce the loop size. The stop member is disposed on the first snapping member for preventing the movable section of the strap from moving backward to the second snapping member. The locking mechanism is mounted on the first snapping member. The locking mechanism is in a locking state when the second snapping member is not allowed to depart from the first snapping member, and in an unlocking state when the second snapping member is allowed to depart from the first snapping member.

公开(公告)号：US20070296729A1

公开(公告)日：2007-12-27

申请号：US11472701

申请日：2006-06-21

申请人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  De Dzwo Hsu

发明人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  De Dzwo Hsu

IPC分类号： G09G5/36

CPC分类号： G06F9/3851 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/384 ,  G06T15/005

摘要： A multi-threaded processor is provided, such as a shader processor, having an internal unified memory space that is shared by a plurality of threads and is dynamically assigned to threads as needed. A mapping table that maps virtual registers to available internal addresses in the unified memory space so that thread registers can be stored in contiguous or non-contiguous memory addresses. Dynamic sizing of the virtual registers allows flexible allocation of the unified memory space depending on the type and size of data in a thread register. Yet another feature provides an efficient method for storing graphics data in the unified memory space to improve fetch and store operations from the memory space. In particular, pixel data for four pixels in a thread are stored across four memory devices having independent input/output ports that permit the four pixels to be read in a single clock cycle for processing.

摘要翻译： 提供了多线程处理器，例如着色器处理器，具有由多个线程共享的内部统一存储器空间，并且根据需要动态分配给线程。 映射表将虚拟寄存器映射到统一存储空间中的可用内部地址，以便线程寄存器可以存储在连续或不连续的存储器地址中。 虚拟寄存器的动态大小允许根据线程寄存器中数据的类型和大小灵活分配统一存储空间。 另一个特征提供了用于将统计存储器空间中的图形数据存储以改善从存储器空间获取和存储操作的有效方法。 特别地，线程中的四个像素的像素数据被存储在具有独立输入/输出端口的四个存储器件中，这些存储器件允许以单个时钟周期读取四个像素进行处理。

公开(公告)号：US20070282928A1

公开(公告)日：2007-12-06

申请号：US11448272

申请日：2006-06-06

申请人： Guofang Jiao ,  Yun Du ,  Chun Yu

发明人： Guofang Jiao ,  Yun Du ,  Chun Yu

IPC分类号： G06F17/30

CPC分类号： G06F12/0875 ,  G06F9/485

摘要： In general, the disclosure is directed to techniques for controlling stack overflow. The techniques described herein utilize a portion of a common cache or memory located outside of the processor core as a stack extension. A processor core monitors a stack within the processor core and transfers the content of the stack to the stack extension outside of the processor core when the processor core stack exceeds a maximum number of entries. When the processor core determines the stack within the processor core falls below a minimum number of entries the processor core transfers at least a portion of the content maintained in the stack extension into the stack within the processor core. The techniques prevent malfunction and crash of threads executing within the processor core by utilizing stack extensions outside of the processor core.

摘要翻译： 通常，本公开涉及用于控制堆栈溢出的技术。 本文描述的技术利用位于处理器核心外部的公共高速缓存或存储器的一部分作为堆栈扩展。 当处理器核心堆栈超过最大数量的条目时，处理器核心监视处理器核心内的堆栈并将堆栈的内容传输到处理器核心外部的堆栈扩展。 当处理器核心确定处理器核心内的堆栈低于最小数量的条目时，处理器核心将保持在堆栈扩展中的内容的至少一部分传输到处理器核心内的堆栈中。 该技术通过利用处理器核心外部的堆栈扩展来防止在处理器核心内执行的线程的故障和崩溃。

公开(公告)号：US20070273698A1

公开(公告)日：2007-11-29

申请号：US11441696

申请日：2006-05-25

申请人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  Alexei V. Bourd

发明人： Yun Du ,  Guofang Jiao ,  Chun Yu ,  Alexei V. Bourd

IPC分类号： G06T1/00

CPC分类号： G06T1/20 ,  G06F9/30167 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3885

摘要： A graphics processor capable of efficiently performing arithmetic operations and computing elementary functions is described. The graphics processor has at least one arithmetic logic unit (ALU) that can perform arithmetic operations and at least one elementary function unit that can compute elementary functions. The ALU(s) and elementary function unit(s) may be arranged such that they can operate in parallel to improve throughput. The graphics processor may also include fewer elementary function units than ALUs, e.g., four ALUs and a single elementary function unit. The four ALUs may perform an arithmetic operation on (1) four components of an attribute for one pixel or (2) one component of an attribute for four pixels. The single elementary function unit may operate on one component of one pixel at a time. The use of a single elementary function unit may reduce cost while still providing good performance.

摘要翻译： 描述能够有效执行算术运算和计算基本功能的图形处理器。 图形处理器具有至少一个可执行算术运算的算术逻辑单元（ALU）和至少一个可以计算基本功能的基本功能单元。 ALU和基本功能单元可以被布置成使得它们可以并行操作以提高吞吐量。 图形处理器还可以包括比ALU更少的基本功能单元，例如四个ALU和单个基本功能单元。 四个ALU可以对（1）四个像素的属性的四个分量或（2）四个像素的属性的一个分量执行算术运算。 单个基本功能单元可以一次操作一个像素的一个分量。 使用单个基本功能单元可以降低成本，同时仍然提供良好的性能。

公开(公告)号：US20070175247A1

公开(公告)日：2007-08-02

申请号：US11396696

申请日：2006-04-04

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： E05B73/00

CPC分类号： E05B37/0034 ,  E05B35/105 ,  E05B37/025 ,  E05B39/00 ,  Y10T70/5009

摘要： A double lock includes a first lock body including a key lock mechanism, a second lock body movably mounted on the first lock body and including a number lock mechanism, and an indicator movably mounted on the second lock body. The second lock body is lockable and unlockable by either one of the key lock mechanism and the number lock mechanism. When the number lock mechanism misses a correct code, the indicator is driven by the second lock body to an indication position, and when the number lock mechanism reaches the correct code, the indicator is driven by the second lock body to return to an original position. Thus, the double lock has an indication function without having to provide a shackle that is used in the conventional padlock.

摘要翻译： 双锁具有包括钥匙锁定机构的第一锁体，可移动地安装在第一锁体上的第二锁体，包括数字锁定机构，以及可移动地安装在第二锁体上的指示器。 第二锁体通过钥匙锁定机构和数字锁定机构中的任一个可锁定和解锁。 当数字锁定机构错过正确的代码时，指示器被第二锁体驱动到指示位置，并且当数字锁定机构到达正确的代码时，指示器被第二锁体驱动以返回到原始位置 。 因此，双锁具有指示功能，而不必提供在常规挂锁中使用的钩环。

公开(公告)号：US20060254325A1

公开(公告)日：2006-11-16

申请号：US11491258

申请日：2006-07-24

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： E05B37/00

CPC分类号： E05B37/0034 ,  E05B35/105 ,  E05B37/025 ,  E05B37/14 ,  E05B39/00 ,  E05B67/24 ,  Y10T70/415 ,  Y10T70/424 ,  Y10T70/8027

摘要： A padlock comprising a housing, a shackle, a lock mechanism and a movable block. The shackle is mounted on the housing and has a first end formed with a shaft portion movably mounted in the housing, and a second end formed with a locking portion moved with the shaft portion and extended outward from the housing. The lock mechanism is mounted on the housing, and includes a lock core and a limit knob. The lock core is mounted in the housing, and the limit knob is located outside the housing and movable by the lock core so as to engage or disengage with the locking portion of the shackle. The movable block is connected to the limit knob of the lock mechanism so that the movable block can be moved to an indication position by operating the lock core of the lock mechanism.

摘要翻译： 一种挂锁，包括壳体，钩环，锁定机构和可动块。 钩环安装在壳体上，并且具有形成有可移动地安装在壳体中的轴部的第一端，以及形成有与轴部一起移动并从壳体向外延伸的锁定部的第二端。 锁定机构安装在壳体上，并且包括锁芯和限位旋钮。 锁芯安装在壳体中，限位旋钮位于壳体的外部并且可通过锁芯移动，以便与锁扣的锁定部分接合或脱离。 可移动块连接到锁定机构的限位旋钮，使得可动块可以通过操作锁定机构的锁芯而移动到指示位置。

公开(公告)号：US20060107710A1

公开(公告)日：2006-05-25

申请号：US11032116

申请日：2005-01-11

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： E05B37/02

CPC分类号： E05B37/025 ,  Y10T70/415 ,  Y10T70/424 ,  Y10T70/7141 ,  Y10T70/7147 ,  Y10T70/8027 ,  Y10T70/8108 ,  Y10T70/8162

摘要： A padlock includes a housing, a shackle, a number lock mechanism, a key lock mechanism, a movable block, and an identification member. Thus, the identification member is exposed outward from the window of the limit knob after the padlock has been unlocked by an inspector of the customs for checking the luggage so as to remind a user to inspect if contents of the luggage that has been opened and checked are missed or lost.

公开(公告)号：US20060075793A1

公开(公告)日：2006-04-13

申请号：US10962527

申请日：2004-10-13

申请人： Chun Yu

发明人： Chun Yu

IPC分类号： E05B37/02

CPC分类号： E05B37/025 ,  E05B67/003 ,  Y10T70/415 ,  Y10T70/435 ,  Y10T70/483 ,  Y10T70/7141 ,  Y10T70/7147

摘要： A cable lock includes a case having a slot defined through a first side and an opening defined through the second side and being in communication with the slot. A flexible cable has one end fixed to the case and a free end of the flexible cable is removably engaged with the opening and the slot. A combination unit is received in the case includes a shaft movably extending through the combination unit. A top plate is connected to a top of the shaft and has a stop plate which is located inside of the second side and movably blocks the opening. A button is pivotably connected to the case and drives an action plate to push the top plate and the shaft downward so as to remove the stop plate away from the opening, and the free end of the flexible cable is able to remove from the opening.

摘要翻译： 电缆锁包括壳体，壳体具有通过第一侧限定的槽和通过第二侧限定的开口并与槽连通。 柔性电缆的一端固定在壳体上，柔性电缆的自由端可拆卸地与开口和槽接合。 在包括可移动地延伸穿过组合单元的轴的壳体中接收组合单元。 顶板连接到轴的顶部并且具有位于第二侧内侧的止动板，并且可移动地阻挡开口。 按钮可枢转地连接到壳体并驱动动作板以将顶板和轴向下推动，以便将挡板从开口移除，并且柔性电缆的自由端能够从开口移除。

公开(公告)号：US5658995A

公开(公告)日：1997-08-19

申请号：US562842

申请日：1995-11-27

申请人： Joachim B. Kohn ,  Chun Yu

发明人： Joachim B. Kohn ,  Chun Yu

IPC分类号： A61K47/34 ,  A61K47/48 ,  A61L27/00 ,  C08G63/672 ,  C08G63/685 ,  C08G64/16 ,  C08G64/18 ,  C08G69/40 ,  C08L69/00 ,  C08L77/00

CPC分类号： A61K47/48215 ,  A61K47/48192 ,  A61K47/48246 ,  C08G63/6856 ,  C08G64/1641 ,  C08G64/183

摘要： Random block copolymers having the formula: ##STR1## wherein R.sub.1 is --CH.dbd.CH-- or (--CH.sub.2 --).sub.j, in which j is zero or an integer from one to eight; R.sub.2 is selected from hydrogen, straight and branched alkyl and alkylaryl groups containing up to 18 carbon atoms and derivatives or biologically and pharmaceutically active compounds covalently bonded to said copolymer; each R.sub.3 is independently an alkylene group containing up to 4 carbon atoms; y is an integer between about 5 and about 3000; and f is the percent molar fraction of alkylene oxide in the copolymer and ranges between about 1 and about 99 mole percent. Implantable medical devices and drug delivery implants containing the random block copolymers are also disclosed, along with methods for drug delivery and for preventing the formation of adhesions between injured tissues employing the random block copolymers. Polyarylate random block copolymers are also described.

摘要翻译： 其中R 1为-CH = CH-或（-CH 2 - ）j，其中j为0或1至8的整数; R2选自含有至多18个碳原子的氢，直链和支链烷基和烷基芳基以及与所述共聚物共价结合的衍生物或生物和药学活性化合物; 每个R 3独立地是含有至多4个碳原子的亚烷基; y为约5至约3000之间的整数; f是共聚物中环氧烷的摩尔百分比，在约1至约99摩尔％之间。 还公开了含有无规嵌段共聚物的植入式医疗装置和药物递送植入物，以及用于药物递送和用于使用无规嵌段共聚物的损伤组织之间形成粘连的方法。 还描述了聚芳酯无规嵌段共聚物。

公开(公告)号：US09804995B2

公开(公告)日：2017-10-31

申请号：US13007333

申请日：2011-01-14

申请人： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

发明人： Alexei V. Bourd ,  Andrew Gruber ,  Aleksandra L. Krstic ,  Robert J. Simpson ,  Colin Sharp ,  Chun Yu

IPC分类号： G06F15/00 ,  G06F15/76 ,  G06F15/173

CPC分类号： G06F15/17325

摘要： This disclosure describes techniques for extending the architecture of a general purpose graphics processing unit (GPGPU) with parallel processing units to allow efficient processing of pipeline-based applications. The techniques include configuring local memory buffers connected to parallel processing units operating as stages of a processing pipeline to hold data for transfer between the parallel processing units. The local memory buffers allow on-chip, low-power, direct data transfer between the parallel processing units. The local memory buffers may include hardware-based data flow control mechanisms to enable transfer of data between the parallel processing units. In this way, data may be passed directly from one parallel processing unit to the next parallel processing unit in the processing pipeline via the local memory buffers, in effect transforming the parallel processing units into a series of pipeline stages.