Busbar with tailored perforation sizes to provide thermal path

    公开(公告)号:US11527357B2

    公开(公告)日:2022-12-13

    申请号:US17223366

    申请日:2021-04-06

    Abstract: Disclosed is an assembly including a busbar that includes: a first layer that defines: first layer top and bottom surfaces; first layer first and second ends; and a first layer center region between the first layer first and second ends; and the first layer forms first layer perforations of different sizes about the first layer center region so perforations closer to the first layer first end are smaller than perforations spaced apart therefrom; a second layer that is disposed against and electrically isolated from the first layer bottom surface, wherein the second layer defines connector orifices having a same size as each other that are aligned with the first layer perforations; and a first capacitor supported against and electrically connected to the first layer top surface, wherein the first capacitor includes busbar connectors that respectively extend through the first layer perforations to electrically connect with the connector orifices.

    MULTI-FUNCTIONAL CURRENT LIMITER FOR ENERGY STORAGE DEVICES

    公开(公告)号:US20220393489A1

    公开(公告)日:2022-12-08

    申请号:US17342221

    申请日:2021-06-08

    Abstract: Systems for a current limiting circuit are provided. Aspects include a first set of batteries coupled to a battery terminal, a power converter coupled to a power converter terminal, wherein the battery terminal is coupled to the power converter terminal, a first current limiting circuit in series with the first set of batteries, wherein the current limiting circuit comprises a first circuit comprising a first transistor in series with a first diode, a second circuit comprising a second transistor in series with a second diode, a first RL circuit, wherein the first RL circuit, the first circuit, and the second circuit are arranged in parallel, a controller configured to operate the first current limiter in a plurality of modes including a battery discharge mode including the controller operating the first transistor in an off state, and operating the second transistor in a switching state.

    POWER CONVERSION SYSTEMS AND METHODS

    公开(公告)号:US20210297009A1

    公开(公告)日:2021-09-23

    申请号:US16827528

    申请日:2020-03-23

    Abstract: A power conversion system includes a hybrid power converter phase unit including three voltage inputs, a voltage output, a pair of outer switches between the voltage inputs and voltage output, and a pair of inner switches between the voltage inputs and the outer switches. The power conversion system includes a controller in electrical communication with the inner and outer switches. The controller is configured to selectively disable or enable the inner switches by switching the inner switches OFF or ON. A method includes selectively disabling or enabling inner switches in a hybrid power converter phase unit with a controller such that the hybrid power converter phase unit is a 3-level converter when the inner switches are ON and enabled in a 3-level mode and a 2-level converter when the inner switches are OFF and disabled in a 2-level mode.

    DC BUS CAPACITOR BALANCING FOR THREE-LEVEL, SIX-PHASE VOLTAGE SOURCE CONVERTERS

    公开(公告)号:US20200328691A1

    公开(公告)日:2020-10-15

    申请号:US16381366

    申请日:2019-04-11

    Inventor: Lei Xing Xin Wu

    Abstract: Provided are embodiments including a system for balancing DC bus capacitors for converters. The system can include a first 3-phase system, and a second 3-phase system, wherein the first 3-phase system and the second 3-phase system are operably connected. The system can also include one or more DC capacitors coupled to the first 3-phase system and the second 3-phase system, and a controller, wherein the controller is configured to control switching of the first 3-phase system and the second 3-phase system so that an output of second 3-phase system is delayed 60 degrees from an output of the first 3-phase system. Also, embodiments are provided for a method for balancing DC bus capacitors.

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